IP Library › Granted Patent US 11,315,865
Granted Patent B2
US 11,315,865 · App. 17/234,826 · Granted Apr 26, 2022

Circuit board structure and manufacturing method thereof

Inventor: Chien-Chen Lin (Taoyuan, TW)
Assignee: Unimicron Technology Corp.
H01L23/49838H01L21/4857H01L23/49822H05K1/11H05K3/06
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Quick Facts
Patent No.
US 11,315,865
App. No.
17/234,826
Granted
Apr 26, 2022
Kind
B2
Abstract

A method of manufacturing circuit board structure includes forming a sacrificial layer having first openings on a substrate; forming a metal layer on the sacrificial layer; forming a patterned photoresist layer having second openings over the sacrificial layer, in which the second openings are connected to the first openings and expose a portion of the metal layer; forming a first circuit layer filling the second openings and the first openings; forming a first dielectric layer over the sacrificial layer and covering the metal layer, in which the first dielectric layer has third openings exposing the first circuit layer; forming a second circuit layer filling the third openings and covering a portion of the first dielectric layer; removing the substrate to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.

Claims (23)

1. A method of manufacturing a circuit board structure, comprising steps of:

forming a sacrificial layer on a substrate, wherein the sacrificial layer has a first opening exposing a portion of the substrate;

forming a metal layer on a sidewall and a top surface of the sacrificial layer;

forming a patterned photoresist layer over the sacrificial layer, wherein the patterned photoresist layer has a second opening connecting to the first opening and exposing a portion of the metal layer;

forming a first circuit layer filling the second opening and the first opening, wherein the first circuit layer covers the portion of the metal layer;

forming a first dielectric layer over the sacrificial layer and covering the metal layer, wherein the first dielectric layer has a third opening exposing the first circuit layer;

forming a second circuit layer filling the third opening and covering a portion of the first dielectric layer, wherein the second circuit layer is integrally formed without any interface;

removing the substrate to expose the sacrificial layer, a portion of the metal layer, and a portion of the first circuit layer; and

removing the sacrificial layer and the metal layer.

2. The method of claim 1 , wherein the first circuit layer has a first portion located in the first opening and a second portion located in the second opening, while the first portion and the second portion are integrally formed as a unitary structure.

3. The method of claim 1 , wherein the step of forming the metal layer on the sacrificial layer comprises conformally forming the metal layer on the sacrificial layer.

4. The method of claim 1 , wherein the step of forming the patterned photoresist layer over the sacrificial layer comprises:

forming a photoresist layer over the sacrificial layer;

exposing the photoresist layer by using a first light source, wherein the first light source and the sacrificial layer are respectively disposed on opposite sides of the substrate;

exposing the photoresist layer by using a second light source, wherein the second light source is disposed at a side of the substrate on which the sacrificial layer is disposed; and

performing a developing step to form the patterned photoresist layer.

5. The method of claim 4 , wherein the photoresist layer comprises a positive photoresist material.

6. The method of claim 1 , wherein the substrate is made of a light transmissive material.

7. The method of claim 1 , after the step of forming the second circuit layer and before the step of removing the substrate, further comprising:

forming a second dielectric layer over the first dielectric layer and covering the first dielectric layer and the second circuit layer, wherein the second dielectric layer has a fourth opening exposing the second circuit layer; and

forming a third circuit layer filling the fourth opening and covering a portion of the second dielectric layer.

8. The method of claim 1 , after the step of forming the second circuit layer and before the step of removing the substrate, further comprising:

forming a solder mask layer on the first dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2021
From: LIN, CHIEN-CHEN
To: UNIMICRON TECHNOLOGY CORP.
Reel/Frame 055980/0410 →
Priority Claims (1)
TW 108125490 · Jul 18, 2019 · national
Continuity (2)
Division 16579812 · Sep 23, 2019
Related Publication 20210242123A1 · Aug 5, 2021