3D memory semiconductor devices and structures
A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain and a channel; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel includes a circular shape or an ellipsoidal shape.
1. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain and a channel;
a plurality of bit-line pillars,
wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein said bit-line pillars are vertically oriented,
wherein said channel is horizontally oriented, and
wherein said channel comprises a circular shape or an ellipsoidal shape.
2. The device according to claim 1 ,
wherein each of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprise metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
3. The device according to claim 1 ,
wherein each of said memory transistors is directly connected to at least one of said bit-line pillars.
4. The device according to claim 1 ,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or a partially or fully metalized drain.
5. The device according to claim 1 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
6. The device according to claim 1 ,
wherein said channel comprises crystallized polysilicon, and
wherein said crystallized polysilicon has been crystallized from a heat sourced from said source or drain of said channel.
7. The device according to claim 1 ,
wherein at least one of said memory transistors is self-aligned to an overlaying memory transistor, being processed following the same lithography step.
8. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain and a channel;
a plurality of bit-line pillars,
wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein said bit-line pillars are vertically oriented, and
wherein said channel is horizontally oriented and comprises a channel width longer than 5 nm and shorter than 25 nm.
9. The device according to claim 8 ,
wherein each of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprise metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
10. The device according to claim 8 ,
wherein each of said memory transistors is directly connected to at least one of said bit-line pillars.
11. The device according to claim 8 ,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or a partially or fully metalized drain.
12. The device according to claim 8 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
13. The device according to claim 8 ,
wherein said channel comprises a circular shape or an ellipsoidal shape.
14. The device according to claim 8 ,
wherein at least one of said memory transistors is self-aligned to an overlaying memory transistor, being processed following the same lithography step.
15. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain and a channel;
a plurality of bit-line pillars,
wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein said bit-line pillars are vertically oriented,
wherein at least one of said plurality of said memory cells comprise a tunneling oxide thinner than 1 nm, and
wherein at least one of said plurality of said memory cells comprise a tunneling oxide thicker than 3 nm.
16. The device according to claim 15 ,
wherein each of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprise metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
17. The device according to claim 15 ,
wherein each of said memory transistors is directly connected to at least one of said bit-line pillars.
18. The device according to claim 15 ,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or a partially or fully metalized drain.
19. The device according to claim 15 ,
wherein said channel comprises crystallized polysilicon, and
wherein said crystallized polysilicon has been crystallized from a heat sourced from said source or drain of said channel.
20. The device according to claim 15 ,
wherein at least one of said memory transistors is self-aligned to an overlaying memory transistor, being processed following the same lithography step.