Resource sharing in a telecommunications environment
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.
1. A device comprising:
a transceiver including a memory, the memory capable of being shared between an interleaver in a transmit latency path, and a deinterleaver in a receiver latency path;
the transceiver capable of:
being configured with a first impulse noise protection value;
dividing the shared memory between the interleaver and the deinterleaver;
transmitting to another transceiver a first initialization message that indicates the division of the shared memory between the interleaver and the deinterleaver;
being configured with a second impulse noise protection value, that is different than the first impulse noise protection value;
changing the division of the shared memory between the interleaver and the deinterleaver such that one or more bytes of the shared memory that were allocated to the interleaver when the transceiver was configured with the first impulse noise protection value are allocated to the deinterleaver when the transceiver is configured with the second impulse noise protection value; and
transmitting to another transceiver a second initialization message that indicates the changed division of the shared memory between the interleaver and the deinterleaver.
2. The device of claim 1 , wherein the first message indicates a first interleaver depth value and the second message indicates a second interleaver depth value, that is different than the first interleaver depth value.
3. The device of claim 1 , wherein the first message indicates a first deinterleaver depth value and the second message indicates a second deinterleaver depth value, that is different than the first deinterleaver depth value.
4. The device of claim 1 , wherein the first message indicates a first codeword size and the second message indicates a second codeword size, that is different than the first codeword size.
5. A device comprising:
a transceiver including a memory, the memory capable of being shared between an interleaver in a transmit latency path and a deinterleaver in a receiver latency path;
the transceiver capable of:
being configured with a first latency value;
dividing the shared memory between the interleaver and the deinterleaver;
transmitting to another transceiver a first initialization message that indicates the division of the shared memory between the interleaver and the deinterleaver;
being configured with a second latency value, that is different than the first latency value;
changing the division of the shared memory between the interleaver and the deinterleaver such that one or more bytes of the shared memory that were allocated to the interleaver when the transceiver was configured with the first latency value are allocated to the deinterleaver when the transceiver is configured with the second latency value; and
transmitting to another transceiver a second initialization message that indicates the changed division of the shared memory between the interleaver and the deinterleaver.
6. The device of claim 5 , wherein the first message indicates a first interleaver depth value and the second message indicates a second interleaver depth value, that is different than the first interleaver depth value.
7. The device of claim 5 , wherein the first message indicates a first deinterleaver depth value and the second message indicates a second deinterleaver depth value, that is different than the first deinterleaver depth value.
8. The device of claim 5 , wherein the first message indicates a first codeword size and the second message indicates a second codeword size, that is different than the first codeword size.
9. A device comprising:
a transceiver including a memory, the memory capable of being shared between an interleaver in a transmit latency path and a deinterleaver in a receiver latency path;
the transceiver capable of:
being configured with a first data rate value;
dividing the shared memory between the interleaver and the deinterleaver;
transmitting to another transceiver a first initialization message that indicates the division of the shared memory between the interleaver and the deinterleaver;
being configured with a second data rate value, that is different than the first data rate value;
changing the division of the shared memory between the interleaver and the deinterleaver such that one or more bytes of the shared memory that were allocated to the interleaver when the transceiver was configured with the first data rate value are allocated to the deinterleaver when the transceiver is configured with the second data rate value; and
transmitting to another transceiver a second initialization message that indicates the changed division of the shared memory between the interleaver and the deinterleaver.
10. The device of claim 9 , wherein the first message indicates a first interleaver depth value and the second message indicates a second interleaver depth value, that is different than the first interleaver depth value.
11. The device of claim 9 , wherein the first message indicates a first deinterleaver depth value and the second message indicates a second deinterleaver depth value, that is different than the first deinterleaver depth value.
12. The device of claim 9 , wherein the first message indicates a first codeword size and the second message indicates a second codeword size, that is different than the first codeword size.