Bias generating devices and methods for generating bias
The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.
1. A bias voltage generating device, comprising:
a first diode-connected transistor pair connected to receive a first voltage, the first diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor;
a second diode-connected transistor pair connected to receive a second voltage; and
a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair, the first transistor pair configured to generate a third voltage in response to the first voltage and the second voltage,
wherein a drain and a gate of the diode-connected p-type transistor of the first diode-connected transistor pair and a drain and a gate of the diode-connected n-type transistor of the first diode-connected transistor pair are connected to a gate of a n-type transistor of the first transistor pair.
2. The bias voltage generating device of claim 1 , wherein the second diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor.
3. The bias voltage generating device of claim 2 , wherein a drain and a gate of the diode-connected p-type transistor are connected.
4. The bias voltage generating device of claim 2 , wherein a drain and a gate of the diode-connected n-type transistor are connected.
5. The bias voltage generating device of claim 2 , wherein a drain and a gate of the diode-connected p-type transistor and a drain and a gate of the diode-connected n-type transistor are connected.
6. The bias voltage generating device of claim 2 , wherein a drain and a gate of the diode-connected p-type transistor of the second diode-connected transistor pair and a drain and a gate of the diode-connected n-type transistor of the second diode-connected transistor pair are connected to a gate of a p-type transistor of the first transistor pair.
7. The bias voltage generating device of claim 1 , wherein:
the first transistor pair is connected to receive the first voltage and the second voltage;
the first diode-connected transistor pair is connected between a first impedance element and the second diode-connected transistor pair, and
the second diode-connected transistor pair is connected between the first diode-connected transistor pair and a second impedance element.
8. The bias voltage generating device of claim 7 , wherein each of the first and second impedance elements includes a resistor, a long channel p-type MOSFET diode, and a long channel n-type MOSFET diode.
9. The bias voltage generating device of claim 8 , wherein:
the long channel p-type MOSFET diode includes a first p-type transistor and a second p-type transistor;
a gate of the first p-type transistor and a drain and a gate of the second p-type transistor are connected; and
a drain of the first n-type transistor and a source of the first n-type transistor are connected.
10. The bias voltage generating device of claim 8 , wherein:
the long channel n-type MOSFET diode includes a first n-type transistor and a second n-type transistor;
a drain and a gate of the first n-type transistor and a gate of the second n-type transistor are connected; and
a source of the first n-type transistor and a drain of the first n-type transistor are connected.
11. The bias voltage generating device of claim 7 , wherein each of the first and second impedance elements is formed by a resistor and a long channel MOSFET diode.
12. The bias voltage generating device of claim 1 , wherein the first transistor pair includes the n-type transistor and a p-type transistor, and a source of the n-type transistor of the first transistor pair and a source of the p-type transistor of the first transistor pair are connected.
13. The bias voltage generating device of claim 12 , wherein the third voltage is generated at the source of the n-type transistor of the first transistor pair and the source of the p-type transistor of the first transistor pair.
14. The bias voltage generating device of claim 1 , wherein the third voltage is a portion of a difference between the first voltage and the second voltage.
15. A bias voltage generating device, comprising:
a reference bias section connected to receive a first voltage and a second voltage, the reference bias section comprising a first diode-connected transistor pair connected to receive the first voltage and a second diode-connected transistor pair connected to receive the second voltage, the first diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor; and
a driving section connected to the reference bias section, the driving section configured to generate a third voltage in response to the first voltage and the second voltage, the driving section comprising a first transistor pair,
wherein a drain and a gate of the diode-connected p-type transistor of the first diode-connected transistor pair and a drain and a gate of the diode-connected n-type transistor of the first diode-connected transistor pair are connected to a gate of a n-type transistor of the first transistor pair.
16. The bias voltage generating device of claim 15 , wherein the second diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor.
17. The bias voltage generating device of claim 15 , wherein:
the first transistor pair is connected to receive the first voltage and the second voltage;
the first diode-connected transistor pair is connected between a first impedance element and the second diode-connected transistor pair, and
the second diode-connected transistor pair is connected between the first diode-connected transistor pair and a second impedance element.
18. The bias voltage generating device of claim 15 , wherein the first transistor pair includes the n-type transistor and a p-type transistor, and a source of the n-type transistor of the first transistor pair and a source of the p-type transistor of the first transistor pair are connected.
19. A method for manufacturing a bias voltage generating circuit comprising:
forming the bias voltage generating circuit, comprising:
a reference bias section comprising a first diode-connected transistor pair and a second diode-connected transistor pair, the first diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor; and
a driving section connected to the reference bias section, the driving section comprising a first transistor pair, wherein a drain and a gate of the diode-connected p-type transistor of the first diode-connected transistor pair and a drain and a gate of the diode-connected n-type transistor of the first diode-connected transistor pair are connected to a gate of a n-type transistor of the first transistor pair;
supplying a first voltage to the first diode-connected transistor pair;
supplying a second voltage to the second diode-connected transistor pair;
generating a third voltage in response to the first voltage and the second voltage.
20. The method of claim 19 , wherein the second diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor.