Memory system and method for controlling nonvolatile memory
According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
1. A memory system connectable to a host, comprising:
a plurality of nonvolatile memories, each of the nonvolatile memories including a plurality of memory blocks, each of the memory blocks being an erase unit; and
a controller electrically connected to the nonvolatile memories and configured to manage a plurality of parallel units each including memory blocks belonging to different nonvolatile memories, wherein
the controller is configured to:
manage defect information of at least 1-bit information indicative of being defective or undefective for each of the memory blocks of the parallel units;
receive from the host a write command including a user address to identify first data to be written; and
in response to receiving the write command,
select one memory block from undefective memory blocks included in one parallel unit of the parallel units, by referring to the defect information;
determine a write destination location in the selected memory block;
write the first data to the write destination location; and
return a response to the host, the response including an address indicative of both of the selected block and the write destination location, and the user address.
2. The memory system of claim 1 , wherein
the controller is configured to update, after writing the first data to the write destination location, a block management table corresponding to the selected memory block such that a bit map flag corresponding to the write destination location in the selected memory block is changed to a value indicative of validity.
3. The memory system of claim 1 , wherein
the host is configured to:
in response to receiving the response from the memory system, update a logical-to-physical address translation table included in the host such that the address indicative of both of the selected block and the write destination location is associated with the user address.
4. The memory system of claim 3 , wherein
the host is configured to issue a trim command to the memory system after updating the logical-to-physical address translation table, the trim command including an address indicative of a first location in a first memory block where previous data corresponding to the first data are stored, the previous data being data to be invalidated.
5. The memory system of claim 4 , wherein
the controller is configured to:
receive the trim command from the host; and
in response to receiving the trim command, update a block management table corresponding to the first memory block such that a bit map flag corresponding to the first location in the first memory block is changed to a value indicative of invalidity.
6. The memory system of claim 1 , wherein
the write command further includes an identifier of a first domain to which the first data are to be written, the first data, and an information indicative of a length of the first data, and
the first domain is among a plurality of domains, each of the domains including one or more parallel units among the plurality of parallel units.
7. The memory system of claim 1 , wherein
the plurality of nonvolatile memories are a plurality of nonvolatile memory dies.
8. The memory system of claim 1 , wherein
the address indicative of both of the selected block and the write destination location includes an identifier of the nonvolatile memory to which the selected memory block belongs, a block address corresponding to the selected memory block, and an offset from a leading part of the selected memory block to the write destination location.
9. The memory system of claim 8 , wherein
the offset is represented by a page address of a page to which the write destination location belongs, and an in-page offset corresponding to the write destination location.
10. The memory system of claim 1 , wherein
the address indicative of both of the selected block and the write destination location includes a block address corresponding to the one parallel unit, and an offset from a leading part of the one parallel unit to the write destination location.
11. The memory system of claim 10 , wherein
the offset is represented by an identifier of the nonvolatile memory to which the selected memory block belongs, a page address of a page to which the write destination location belongs, and an in-page offset corresponding to the write destination location.
12. The memory system of claim 1 , wherein
the controller is further configured to:
receive from the host a read command to designate the address indicative of both of the selected memory block and the write destination location; and
in response to receiving the read command, read data from the write destination location in the selected memory block, based on the address designated by the read command.
13. The memory system of claim 1 , wherein
the controller is further configured to;
receive from the host a parallel unit allocate request to designate the number of memory blocks capable of parallel access;
in response to receiving the parallel unit allocate request, select a parallel unit including more number of undefective memory blocks than the number of designated memory blocks from the parallel units; and
allocate the selected parallel unit to the host, and
the one parallel unit is the selected parallel unit allocated to the host.
14. The memory system of claim 1 , wherein
the write command further includes a block address corresponding to one parallel unit, and
the controller is further configured to:
select a parallel unit having the block address included in the write command from the parallel units; and
select one memory block from undefective memory blocks included in the selected parallel unit as a memory block to which the first data are to be written, by referring to the defect information.
15. A method of controlling a memory system including a plurality of nonvolatile memories, each of the nonvolatile memories including a plurality of memory blocks, each of the memory blocks being an erase unit, the method comprising:
managing a plurality of parallel units each including memory blocks belonging to different nonvolatile memories;
managing defect information of at least 1-bit information indicative of being defective or undefective for each of the memory of the parallel units;
receiving from a host a write command including a user address to identify first data to be written; and
in response to receiving the write command,
selecting one memory block from undefective memory blocks included in one parallel unit of the parallel units, by referring to the defect information;
determining a write destination location in the selected memory block;
writing the first data to the write destination location; and
returning a response to the host, the response including an address indicative of both of the selected block and the write destination location, and the user address.
16. The method of claim 15 , further comprising:
updating, after writing the first data to the write destination location, a block management table corresponding to the selected memory block such that a bit map flag corresponding to the write destination location in the selected memory block is changed to a value indicative of validity.
17. The method of claim 15 , wherein
after the response is returned to the host, a logical-to-physical address translation table included in the host is update by the host such that the address indicative of both of the selected block and the write destination location is associated with the user address.
18. The method of claim 17 , wherein
after the logical-to-physical address translation table is updated, a trim command is issued to the memory system by the host, the trim command including an address indicative of a first location in a first memory block where previous data corresponding to the first data are stored, the previous data being data to be invalidated.
19. The method of claim 18 , further comprising:
receiving the trim command from the host; and
in response to receiving the trim command, updating a block management table corresponding to the first memory block such that a bit map flag corresponding to the first location in the first memory block is changed to a value indicative of invalidity.
20. The method of claim 15 , wherein
the write command further includes an identifier of a first domain to which the first data are to be written, the first data, and an information indicative of a length of the first data, and
the first domain is among a plurality of domains, each of the domains including one or more parallel units among the plurality of parallel units.
21. The method of claim 15 , wherein
the plurality of nonvolatile memories are a plurality of nonvolatile memory dies.
22. The method of claim 15 , wherein
the address indicative of both of the selected block and the write destination location includes an identifier of the nonvolatile memory to which the selected memory block belongs, a block address corresponding to the selected block, and an offset from a leading part of the selected memory block to the write destination location.
23. The method of claim 22 , wherein
the offset is represented by a page address of a page to which the write destination location belongs, and an in-page offset corresponding to the write destination location.
24. The method of claim 15 , wherein
the address indicative of both of the selected block and the write destination location includes a block address corresponding to the one parallel unit, and an offset from a leading part of the one parallel unit to the write destination location.
25. The method of claim 24 , wherein
the offset is represented by an identifier of the nonvolatile memory die to which the selected memory block belongs, a page address of a page to which the write destination location belongs, and an in-page offset corresponding to the write destination location.
26. The method of claim 15 , further comprising:
receiving from the host a read command to designate the address indicative of both of the selected memory block and the write destination location; and
in response to receiving the read command, reading data from the write destination location in the selected memory block, based on the address designated by the read command.
27. The method of claim 15 , further comprising:
receiving from the host a parallel unit allocate request to designate the number of memory blocks capable of parallel access;
in response to receiving the parallel unit allocate request, selecting a parallel unit including more number of undefective memory blocks than the number of designated memory blocks from the parallel units; and
allocating the selected parallel unit to the host,
wherein the one parallel unit is the selected parallel unit allocated to the host.
28. The method of claim 15 , wherein
the write command further includes a block address corresponding to one parallel unit, and
the method further comprises:
selecting a parallel unit having the block address included in the write command from the parallel units; and
selecting one memory block from undefective memory blocks included in the selected parallel unit as a memory block to which the first data are to be written, by referring to the defect information.