Method of forming semiconductor device including distributed write driving arrangement
A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.
1. A method of fabricating a distributed write driving arrangement for a semiconductor memory device, the method comprising:
forming bit cells in a first device layer;
forming a local write driver in the first device layer;
forming a local write bit (LWB) line in a first metallization layer over the first device layer;
forming a local write bit_bar (LWB_bar) line in the first metallization layer;
connecting each of the bit cells correspondingly between the LWB and LWB_bar lines;
connecting the local write driver to the LWB line and the LWB_bar line;
forming a global write bit (GWB) line in a second metallization layer over the first metallization layer;
connecting the GWB line to the LWB line;
forming a global write bit_bar (GWBL_bar) line in the second metallization layer;
connecting the GWB line to the LWB line;
connecting the GWBL_bar line to the LWB_bar line;
forming a global write driver in a second device layer; and
connecting the global write driver to the GWB line and the GWBL_bar line.
2. The method of claim 1 , wherein:
the forming bit cells in a first device layer includes:
arranging the bit cells in a column of segments, each segment including corresponding ones of the bit cells; and
the forming a local write driver includes:
locating each local write driver at an interior location in the corresponding segment.
3. The method of claim 1 , further comprising:
arranging the first metallization layer between the first device layer and the second device layer; and
arranging the second metallization layer being between the first metallization layer and the second device layer.
4. The method of claim 1 , wherein:
maximum speed is a parameter representing maximum operational speed of a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have substantially the same footprint as compared to the global write driver.
5. The method of claim 4 , wherein:
footprint is a parameter representing an area consumed by a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have a smaller footprint as compared to the global write driver.
6. The method of claim 1 , wherein:
footprint is a parameter representing an area consumed by a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have a smaller footprint as compared to the global write driver.
7. The method of claim 1 , wherein:
the forming a local write driver includes:
forming a first equalizer circuit;
connecting the first equalizer circuit between the LWB line and the LWB_bar line; and
configuring the first equalizer circuit to be controlled by signals correspondingly on the GWB line and the GWB_bar line; and
the forming a global write driver includes:
forming a second equalizer circuit; and
configuring the second equalizer circuit in a driver-coupling arrangement between the LWB line and the LWB_bar line; and
configuring the second equalizer circuit in a control-coupling arrangement with respect to signals correspondingly on the GWB line and the GWB_bar line.
8. The method of claim 7 , wherein:
forming a first equalizer circuit includes:
forming the first equalizer circuit in the first device layer; and
the forming a second equalizer circuit includes:
forming the second equalizer circuit in a second device layer, the second device layer being above the first device layer.
9. A method of fabricating a distributed write driving arrangement for a semiconductor memory device, the method comprising:
forming bit cells in a first device layer;
forming a local write driver;
forming a local write bit (LWB) line in a first metallization layer over the first device layer;
forming a local write bit_bar (LWB_bar) line in the first metallization layer;
connecting each of the bit cells correspondingly between the LWB and LWB_bar lines;
connecting the local write driver to the LWB line and the LWB_bar line;
forming a global write bit (GWB) line in a second metallization layer over the first metallization layer;
connecting the GWB line to the LWB line;
forming a global write bit_bar (GWBL_bar) line in the second metallization layer;
connecting the GWB line to the LWB line;
connecting the GWBL_bar line to the LWB_bar line;
forming a global write driver; and
connecting the global write driver to the GWB line and the GWBL_bar line; and
wherein:
the forming a local write driver includes:
forming a first equalizer circuit;
connecting the first equalizer circuit between the LWB line and the LWB_bar line; and
configuring the first equalizer circuit to be controlled by signals correspondingly on the GWB line and the GWB_bar line; and
the forming a global write driver includes:
forming a second equalizer circuit; and
configuring the second equalizer circuit in a driver-coupling arrangement between the LWB line and the LWB_bar line; and
configuring the second equalizer circuit in a control-coupling arrangement with respect to signals correspondingly on the GWB line and the GWB_bar line.
10. The method of claim 9 , wherein:
the forming a first equalizer circuit includes:
forming the first equalizer circuit in the first device layer; and
the forming a second equalizer circuit includes:
forming the second equalizer circuit in a second device layer, the second device layer being above the first device layer.
11. The method of claim 9 , wherein:
the forming bit cells in a first device layer includes:
arranging the bit cells in a column of segments, each segment including corresponding ones of the bit cells; and
the forming a local write driver includes:
locating each local write driver at an interior location in the corresponding segment.
12. The method of claim 9 , further comprising:
arranging the first metallization layer between the first device layer and a second device layer; and
arranging the second metallization layer being between the first metallization layer and the second device layer.
13. The method of claim 9 , wherein:
maximum speed is a parameter representing maximum operational speed of a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have substantially the same footprint as compared to the global write driver.
14. The method of claim 13 , wherein:
footprint is a parameter representing an area consumed by a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have a smaller footprint as compared to the global write driver.
15. The method of claim 9 , wherein:
footprint is a parameter representing an area consumed by a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have a smaller footprint as compared to the global write driver.
16. A method of fabricating a distributed write driving arrangement for a semiconductor memory device, the method comprising:
forming bit cells in a first device layer, the bit cells being arranged in a column of segments, each segment including corresponding ones of the bit cells;
forming a local write driver in the first device layer, the forming a local write driver including:
locating each local write driver at an interior location in the corresponding segment;
forming a local write bit (LWB) line in a first metallization layer over the first device layer;
forming a local write bit_bar (LWB_bar) line in the first metallization layer;
connecting each of the bit cells correspondingly between the LWB and LWB_bar lines;
connecting the local write driver to the LWB line and the LWB_bar line;
forming a global write bit (GWB) line in a second metallization layer over the first metallization layer;
connecting the GWB line to the LWB line;
forming a global write bit_bar (GWBL_bar) line in the second metallization layer;
connecting the GWB line to the LWB line;
connecting the GWBL_bar line to the LWB_bar line;
forming a global write driver in a second device layer; and
connecting the global write driver to the GWB line and the GWBL_bar line.
17. The method of claim 16 , further comprising:
arranging the first metallization layer between the first device layer and the second device layer; and
arranging the second metallization layer being between the first metallization layer and the second device layer.
18. The method of claim 16 , wherein:
maximum speed is a parameter representing maximum operational speed of a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have substantially the same footprint as compared to the global write driver.
19. The method of claim 18 , wherein:
footprint is a parameter representing an area consumed by a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have a smaller footprint as compared to the global write driver.
20. The method of claim 16 , wherein:
footprint is a parameter representing an area consumed by a corresponding circuit; and
the forming a local write driver includes:
configuring the local write driver to have a smaller footprint as compared to the global write driver.