IP Library Granted Patent US 11,968,826
Granted Patent B2
US 11,968,826 · App. 17/244,186 · Granted Apr 23, 2024

Three-dimensional memory device with metal-barrier-metal word lines and methods of making the same

Inventors: Ramy Nashed Bassely Said (San Jose, CA); Raghuveer S. Makala (Campbell, CA); Senaka Kanakamedala (San Jose, CA); Rahul Sharangpani (Fremont, CA)
Assignee: SANDISK TECHNOLOGIES LLC
H10B41/27H10B41/10H10B41/35H10B43/10H10B43/27H10B43/35
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Quick Facts
Patent No.
US 11,968,826
App. No.
17/244,186
Granted
Apr 23, 2024
Kind
B2
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures, an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers, and a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers. The memory opening fill structures are formed after performing a halogen outgassing anneal through the memory openings to reduce or eliminate the halogen outgassing damage in the layers of the memory film.

Claims (46)

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

memory openings extending through the alternating stack; and

memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film,

wherein each of the electrically conductive layers comprises:

a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures;

an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers; and

a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers;

wherein the tubular metallic liner comprises tungsten doped with silicon, and the metallic fill material layer comprises tungsten that contains no silicon or has a lower concentration of silicon than the tubular metallic liner; and

wherein an average atomic percentage of silicon within the tubular metallic liner is in a range from 0.1% to 5.0%.

2. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

memory openings extending through the alternating stack; and

memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film,

wherein each of the electrically conductive layers comprises:

a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures;

an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers; and

a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers;

wherein the tubular metallic liner comprises tungsten doped with boron, and the metallic fill material layer comprises tungsten that contains no boron or has a lower concentration of boron than the tubular metallic liner; and

wherein an average atomic percentage of boron within the tubular metallic liner is in a range from 0.1% to 5.0%.

3. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

memory openings extending through the alternating stack; and

memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film,

wherein each of the electrically conductive layers comprises:

a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures;

an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers; and

a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers;

wherein the tubular metallic liners comprise:

a cylindrical outer sidewall having a closed upper edge and a closed lower edge; and

an inner sidewall including a straight inner sidewall segment, an upper tilted convex surface segment connecting an upper edge of the straight inner sidewall segment to the closed upper edge of the cylindrical outer sidewall, and a lower tilted convex surface segment connecting a lower edge of the straight inner sidewall segment to the closed lower edge of the cylindrical outer sidewalk;

wherein the tubular metallic liner has a greater vertical extent than the metallic fill material layer; and

wherein:

each of the memory films comprises a respective aluminum oxide blocking dielectric layer and a respective memory material layer; and

the respective aluminum oxide blocking dielectric layer and the respective memory material layer have a lesser maximum lateral extent at a level of one of the electrically conductive layers than at a level of an insulating layer contacting a top surface of the one of the electrically conductive layers and than at a level of another insulating layer contacting a bottom surface of the one of the electrically conductive layers.

4. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

memory openings extending through the alternating stack; and

memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film,

wherein each of the electrically conductive layers comprises:

a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures;

an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers; and

a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers; and

wherein each of the memory opening fill structures comprises a respective vertical stack of nucleation material liners that contact a respective one of the insulating layers.

5. The three-dimensional memory device of claim 4 , wherein the respective vertical stack of nucleation material liners is vertically interlaced with a respective vertical stack of tubular metallic liners that is a respective subset of the tubular metallic liners within the electrically conductive layers.

6. The three-dimensional memory device of claim 4 , wherein the nucleation material liners comprise a semiconductor material, boron, boron nitride, or a boron-silicon alloy.

Assignments (4)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2021
From: SAID, RAMY NASHED BASSELY; MAKALA, RAGHUVEER S; KANAKAMEDALA, SENAKA; SHARANGPANI, RAHUL
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 056085/0368 →
Continuity (1)
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