Automated geometry optimization for analog, mixed-signal circuit design
A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.
1 . A non-transitory program storage device comprising instructions stored thereon to cause one or more processors to:
receive an indication of a sub-circuit type and a set of sub-circuit performance parameter values, wherein the set of sub-circuit performance parameter values includes a target impedance or a target conductance for a sub-circuit;
determine a sub-circuit topology based on the sub-circuit type and the set of sub-circuit performance parameter values, wherein the sub-circuit topology includes an electrical component;
determine a set of sub-circuit physical parameter values including a dimension of the electrical component using a machine learning (ML) model of the sub-circuit topology and the set of sub-circuit performance parameter values;
generate a data object representing the sub-circuit based on the determined set of sub-circuit physical parameter values and the determined sub-circuit topology; and
output the data object.
2 . The non-transitory program storage device of claim 1 , wherein the instructions for determining the sub-circuit topology further cause the one or more processors to:
receive a set of sub-circuit topologies;
generate sets of sub-circuit parameter values based on sub-circuit topologies of the set of sub-circuit topologies; and
select a sub-circuit topology from the set of sub-circuit topologies based on an optimization function and the sets of sub-circuit parameter values.
3 . The non-transitory program storage device of claim 2 , wherein the optimization function comprises at least one of a cost function, loss function, a number of electrical components of sub-circuit topologies from the set of sub-circuit topologies, or a determination that sub-circuit physical parameter values of sub-circuit topologies from the set of sub-circuit topologies are within predetermined ranges.
4 . The non-transitory program storage device of claim 1 , wherein the sub-circuit physical parameter values include at least a width and length of electrical components of the respective sub-circuit.
5 . The non-transitory program storage device of claim 1 , wherein the ML model is trained to determine sub-circuit physical parameter values for the sub-circuit topology based on sub-circuit performance parameters of the sub-circuit type.
6 . The non-transitory program storage device of claim 5 , wherein the ML model is trained based on simulations of one or more configurations of the sub-circuit topology for a process technology.
7 . The non-transitory program storage device of claim 1 , wherein the set of sub-circuit physical parameter values include a length and a width of the electrical component.
8 . The non-transitory program storage device of claim 1 , wherein the instructions to generate the data object include instructions to generate a netlist representation of the sub-circuit.
9 . An electronic device, comprising:
a memory; and
one or more processors operatively coupled to the memory, wherein the one or more processors are configured to execute instructions causing the one or more processors to:
receive an indication of a sub-circuit type and a set of sub-circuit performance parameter values, wherein the set of sub-circuit performance parameter values includes a target impedance or a target conductance for a sub-circuit;
determine a sub-circuit topology based on the sub-circuit type and the set of sub-circuit performance parameter values, wherein the sub-circuit topology includes an electrical component;
determine a set of sub-circuit physical parameter values including a dimension of the electrical component using a machine learning (ML) model of the sub-circuit topology and the set of sub-circuit performance parameter values;
generate a data object representing the sub-circuit based on the determined set of sub-circuit physical parameter values and the determined sub-circuit topology; and
output the data object.
10 . The electronic device of claim 9 , wherein the instructions for determining the sub-circuit topology further cause the one or more processors to:
receive a set of sub-circuit topologies;
generate sets of sub-circuit parameter values based on sub-circuit topologies of the set of sub-circuit topologies; and
select a sub-circuit topology from the set of sub-circuit topologies based on an optimization function and the sets of sub-circuit parameter values.
11 . The electronic device of claim 10 , wherein the optimization function comprises at least one of a cost function, loss function, a number of electrical components of sub-circuit topologies from the set of sub-circuit topologies, or a determination that sub-circuit physical parameter values of sub-circuit topologies from the set of sub-circuit topologies are within predetermined ranges.
12 . The electronic device of claim 9 , wherein the sub-circuit physical parameter values include at least a width and length of electrical components of the respective sub-circuit.
13 . The electronic device of claim 9 , wherein the ML model is trained to determine sub-circuit physical parameter values for the sub-circuit topology based on sub-circuit performance parameters of the sub-circuit type.
14 . The electronic device of claim 13 , wherein the ML model is trained based on simulations of one or more configurations of the sub-circuit topology for a process technology.
15 . The electronic device of claim 9 , wherein the set of sub-circuit physical parameter values include a length and a width of the electrical component.
16 . The electronic device of claim 9 , wherein the instructions for generating the data object include instructions for generating a netlist representation of the sub-circuit.
17 . A non-transitory program storage device comprising instructions stored thereon to cause one or more processors to:
receive an indication of a sub-circuit type and a set of sub-circuit performance parameter values, wherein the set of sub-circuit performance parameter values includes a target impedance or a target conductance for a sub-circuit;
determine a sub-circuit topology based on the sub-circuit type, the set of sub-circuit performance parameter values, and an optimization function, wherein the sub-circuit topology includes an electrical component, and wherein the optimization function comprises at least one of a cost function, loss function, a number of electrical components;
determine a set of sub-circuit physical parameter values including a width and a length of the electrical component using a machine learning (ML) model of the sub-circuit topology and the set of sub-circuit performance parameter values;
generate a netlist representing the sub-circuit based on the determined set of sub-circuit physical parameter values and the determined sub-circuit topology; and
output the netlist.
18 . The non-transitory program storage device of claim 17 , wherein the ML model is trained to determine sub-circuit physical parameter values for the sub-circuit topology based on sub-circuit performance parameters of the sub-circuit type.
19 . The non-transitory program storage device of claim 18 , wherein the ML model is trained based on simulations of one or more configurations of the sub-circuit topology for a process technology.