Memory component having internal read-modify-write operation

1. A method of operation in a memory component, the method comprising:

receiving a first memory command having an associated first read address indicating a first location in a memory bank of the memory component;

receiving, after receiving the first memory command, a second memory command having an associated second read address indicating a second location in the memory bank of the memory component;

performing first memory operations associated with the first and second memory commands on data at the first and second locations in the memory bank;

modifying the data from the first and second locations in the memory bank to produce first and second modified data; and

performing, after the first memory operations, second memory operations associated with the first and second memory commands using the first and second modified data.

2. The method of claim 1 , wherein performing the first memory operations associated with the first and second memory commands comprises:

accessing first read data from the first location in the memory bank and second read data from the second location in the memory bank; and

receiving first write data associated with the first memory command and second write data associated with the second memory command.

3. The method of claim 2 , wherein modifying the data from the first and second locations in the memory bank comprises:

merging the first received write data with the first read data to form the first modified data;

merging the second received write data with the second read data to form the second modified data.

4. The method of claim 3 , wherein performing the second memory operations associated with the first and second memory commands comprises:

writing the first modified data to the first location in the memory bank; and

writing, after accessing the second read data from the second location in the memory bank, the second modified data to the second location in the memory bank.

5. The method of claim 1 , further comprising:

decoding the data at the first and second locations in the memory bank prior to modifying the data to produce the first and second modified data, wherein decoding the data comprises correcting single bit errors in the data using an error syndrome in the data.

6. The method of claim 1 , wherein modifying the data from the first and second locations in the memory bank comprises combining the data using a data mask.

7. The method of claim 1 , further comprising:

encoding the first and second modified data prior to performing the second memory operations, wherein encoding the first and second modified data comprises generating an error syndrome for the first and second modified data.

8. A memory component comprising:

a memory bank;

processing logic coupled to the memory bank, wherein the processing logic is configured to:

receive a first memory command having an associated first read address indicating a first location in a memory bank of the memory component;

receive, after receiving the first memory command, a second memory command having an associated second read address indicating a second location in the memory bank of the memory component;

perform first memory operations associated with the first and second memory commands on data at the first and second locations in the memory bank;

modify the data from the first and second locations in the memory bank to produce first and second modified data; and

perform, after the first memory operations, second memory operations associated with the first and second memory commands using the first and second modified data.

9. The memory component of claim 8 , wherein to perform the first memory operations associated with the first and second memory commands, the processing logic is configured to:

access first read data from the first location in the memory bank and second read data from the second location in the memory bank; and

receive first write data associated with the first memory command and second write data associated with the second memory command.

10. The memory component of claim 9 , wherein to modify the data from the first and second locations in the memory bank, the processing logic is configured to:

merge the first received write data with the first read data to form the first modified data;

merge the second received write data with the second read data to form the second modified data.

11. The memory component of claim 10 , wherein to perform the second memory operations associated with the first and second memory commands, the processing logic is configured to:

write the first modified data to the first location in the memory bank; and

write, after accessing the second read data from the second location in the memory bank, the second modified data to the second location in the memory bank.

12. The memory component of claim 8 , wherein the processing logic is further configured to:

decode the data at the first and second locations in the memory bank prior to modifying the data to produce the first and second modified data, wherein decoding the data comprises correcting single bit errors in the data using an error syndrome in the data.

13. The memory component of claim 8 , wherein to modify the data from the first and second locations in the memory bank, the processing logic is configured to combine the data using a data mask.

14. The memory component of claim 8 , wherein the processing logic is further configured to:

encode the first and second modified data prior to performing the second memory operations, wherein encoding the first and second modified data comprises generating an error syndrome for the first and second modified data.

15. A memory component comprising:

a memory bank;

a command interface coupled to the memory bank, the command interface to receive a first memory command having an associated first read address indicating a first location in the memory bank, and to receive, after receiving the first memory command, a second memory command having an associated second read address indicating a second location in the memory bank;

a data interface coupled to the memory bank, the data interface to perform first memory operations associated with the first and second memory commands on data at the first and second locations in the memory bank; and

an error correction circuit coupled to the data interface and to the memory bank, the error correction circuit to modify the data from the first and second locations in the memory bank to produce first and second modified data, and to perform, after the first memory operations, second memory operations associated with the first and second memory commands using the first and second modified data.

16. The memory component of claim 15 , wherein to perform the first memory operations associated with the first and second memory commands, the data interface is to:

access first read data from the first location in the memory bank and second read data from the second location in the memory bank; and

receive first write data associated with the first memory command and second write data associated with the second memory command.

17. The memory component of claim 16 , wherein to modify the data from the first and second locations in the memory bank, the error correction circuit is to:

merge the first received write data with the first read data to form the first modified data; and

merge the second received write data with the second read data to form the second modified data.

18. The memory component of claim 17 , wherein to perform the second memory operations associated with the first and second memory commands, the error correction circuit is to:

write the first modified data to the first location in the memory bank; and

write, after accessing the second read data from the second location in the memory bank, the second modified data to the second location in the memory bank.

19. The memory component of claim 15 , wherein the data interface is further to:

decode the data at the first and second locations in the memory bank prior to modifying the data to produce the first and second modified data, wherein to decode the data, the data interface is to correct single bit errors in the data using an error syndrome in the data.

20. The memory component of claim 15 , wherein to modify the data from the first and second locations in the memory bank, the error correction circuit is to combine the data using a data mask.