IP Library › Granted Patent US 11,610,998
Granted Patent B2
US 11,610,998 · App. 17/257,364 · Granted Mar 21, 2023

Semiconductor device

Inventors: Rai Sato (Tochigi, JP); Masami Jintyou (Shimotsuga, JP); Masayoshi Dobashi (Shimotsuga, JP); Takashi Shiraishi (Tochigi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869G02F1/136277H01L27/127H01L27/1225H01L29/66742H01L29/66969H01L29/78651H01L29/78696
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Quick Facts
Patent No.
US 11,610,998
App. No.
17/257,364
Granted
Mar 21, 2023
Kind
B2
Abstract

A transistor in which shape defects are unlikely to occur is provided. A transistor with favorable electrical characteristics is provided. A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a transistor. The transistor includes a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. The first insulating layer is positioned over the semiconductor layer. The metal oxide layer is positioned over the first insulating layer. The functional layer is positioned over the metal oxide layer. The conductive layer is positioned over the functional layer. The semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions overlapping with each other. In the channel length direction of the transistor, end portions of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inward from an end portion of the semiconductor layer. An etching rate of the functional layer with an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid is lower than an etching rate of the conductive layer.

Claims (57)

1. A semiconductor device comprising a transistor,

wherein the transistor comprises a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, a conductive layer, and a second insulating layer,

wherein the first insulating layer is positioned over the semiconductor layer,

wherein the metal oxide layer is positioned over the first insulating layer,

wherein the functional layer is positioned over the metal oxide layer,

wherein the conductive layer is positioned over the functional layer,

wherein the second insulating layer is provided over the conductive layer,

wherein the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions overlapping with each other,

wherein in a channel length direction of the transistor, end portions of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inward from an end portion of the semiconductor layer,

wherein in the channel length direction of the transistor, end portions of the metal oxide layer, the functional layer, and the conductive layer are positioned inward from the end portion of the first insulating layer,

wherein in the channel length direction of the transistor, the end portion of the conductive layer is positioned inward from the end portions of the metal oxide layer and the functional layer,

wherein the second insulating layer is in contact with a top surface of the first insulating layer, and

wherein an etching rate of the functional layer with an etchant is lower than an etching rate of the conductive layer.

2. The semiconductor device according to claim 1 ,

wherein the metal oxide layer and the functional layer have substantially same top surface shapes.

3. The semiconductor device according to claim 1 ,

wherein the semiconductor layer comprises a first region not overlapping with the first insulating layer,

wherein the second insulating layer is in contact with the first region, and

wherein the second insulating layer comprises silicon, nitrogen, and hydrogen.

4. A semiconductor device comprising a transistor,

wherein the transistor comprises a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, a conductive layer, and a second insulating layer,

wherein the first insulating layer is positioned over the semiconductor layer,

wherein the metal oxide layer is positioned over the first insulating layer,

wherein the functional layer is positioned over the metal oxide layer,

wherein the conductive layer is positioned over the functional layer,

wherein the second insulating layer is provided over the conductive layer,

wherein the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions overlapping with each other,

wherein in a channel length direction of the transistor, end portions of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inward from an end portion of the semiconductor layer,

wherein in the channel length direction of the transistor, end portions of the metal oxide layer, the functional layer, and the conductive layer are positioned inward from the end portion of the first insulating layer,

wherein in the channel length direction of the transistor, the end portion of the conductive layer is positioned inward from the end portions of the metal oxide layer and the functional layer,

wherein the second insulating layer is in contact with a top surface of the first insulating layer, and

wherein an etching rate of the functional layer with an etchant containing hydrogen peroxide is lower than an etching rate of the conductive layer.

5. The semiconductor device according to claim 4 ,

wherein the metal oxide layer and the functional layer have substantially same top surface shapes.

6. The semiconductor device according to claim 4 ,

wherein the semiconductor layer comprises a first region not overlapping with the first insulating layer,

wherein the second insulating layer is in contact with the first region, and

wherein the second insulating layer comprises silicon, nitrogen, and hydrogen.

7. A semiconductor device comprising a transistor,

wherein the transistor comprises a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, a conductive layer, and a second insulating layer,

wherein the first insulating layer is positioned over the semiconductor layer,

wherein the metal oxide layer is positioned over the first insulating layer,

wherein the functional layer is positioned over the metal oxide layer,

wherein the conductive layer is positioned over the functional layer,

wherein the second insulating layer is provided over the conductive layer,

wherein the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions overlapping with each other,

wherein in a channel length direction of the transistor, end portions of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inward from an end portion of the semiconductor layer,

wherein in the channel length direction of the transistor, end portions of the metal oxide layer, the functional layer, and the conductive layer are positioned inward from the end portion of the first insulating layer,

wherein in the channel length direction of the transistor, the end portion of the conductive layer is positioned inward from the end portions of the metal oxide layer and the functional layer,

wherein the second insulating layer is in contact with a top surface of the first insulating layer, and

wherein an etching rate of the functional layer with an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid is lower than an etching rate of the conductive layer.

8. The semiconductor device according to claim 7 ,

wherein the metal oxide layer and the functional layer have substantially same top surface shapes.

9. The semiconductor device according to claim 7 ,

wherein the semiconductor layer comprises a first region not overlapping with the first insulating layer,

wherein the second insulating layer is in contact with the first region, and

wherein the second insulating layer comprises silicon, nitrogen, and hydrogen.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2020
From: SATO, RAI; JINTYOU, MASAMI; DOBASHI, MASAYOSHI; SHIRAISHI, TAKASHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 054783/0939 →
Priority Claims (2)
JP JP2018-129881 · Jul 9, 2018 · national
JP JP2018-141720 · Jul 27, 2018 · national
Continuity (1)
Related Publication 20210126132A1 · Apr 29, 2021
Cited By (2)
US 12,191,316 US 12,648,319