IP Library › Granted Patent US 12,191,316
Granted Patent B2
US 12,191,316 · App. 18/439,855 · Granted Jan 7, 2025

Semiconductor device

Inventors: Tatsuya Toda (Tokyo, JP); Toshinari Sasaki (Tokyo, JP); Masayoshi Fuchi (Tokyo, JP)
Assignee: Japan Display Inc.
H01L27/124G02F1/136227G02F1/136286G02F1/1368G09G3/3225G09G3/3266H01L27/1259H10K59/123H10K59/124H10K59/131G02F1/136295G09G2300/0861H01L27/1225H01L27/1255H10K59/1201
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Quick Facts
Patent No.
US 12,191,316
App. No.
18/439,855
Granted
Jan 7, 2025
Kind
B2
Abstract

A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

Claims (22)

1. A semiconductor device comprising:

a first gate electrode;

a first gate insulating layer above the first gate electrode;

a first oxide semiconductor layer above the first gate insulating layer;

a source electrode and a drain electrode connected to the first oxide semiconductor layer;

a second gate insulating layer above the first oxide semiconductor layer;

a second gate electrode above the second gate insulating layer;

a first insulating layer above the second gate electrode;

a second oxide semiconductor layer between the second gate insulating layer and the second gate electrode;

a first aperture penetrating the first insulating layer and the second gate insulating layer, a part of the first aperture overlapping the second oxide semiconductor layer in a planar view;

a first connecting electrode in the first aperture;

a second aperture penetrating the first gate insulating layer; and

a second connecting electrode in the second aperture,

wherein

the first connecting electrode is connected to the second gate electrode and the second connecting electrode, and

the second connecting electrode is connected to the first gate electrode.

2. The semiconductor device according to claim 1 , wherein the first connecting electrode covers a side surface of the second oxide semiconductor layer in the first aperture.

3. The semiconductor device according to claim 1 , wherein the second connecting electrode is in a same layer with the source electrode or the drain electrode.

4. The semiconductor device according to claim 1 , wherein

the second connecting electrode is in contact with a top surface of the first gate insulating layer, and

the source electrode or the drain electrode is in contact with a top surface of the first gate insulating layer.

5. The semiconductor device according to claim 1 , wherein the first connecting electrode is in contact with the second oxide semiconductor layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2024
From: TODA, TATSUYA; SASAKI, TOSHINARI; FUCHI, MASAYOSHI
To: JAPAN DISPLAY INC.
Reel/Frame 066582/0500 →
Priority Claims (1)
JP 2018-067326 · Mar 30, 2018 · national
Continuity (3)
Continuation 17031999 · Sep 25, 2020
Continuation PCTJP2019007661 · Feb 27, 2019
Related Publication 20240258331A1 · Aug 1, 2024
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