IP Library › Granted Patent US 12,677,497
Granted Patent B2
US 12,677,497 · App. 17/259,949 · Granted Jul 7, 2026

Semiconductor device

Inventors: Kan Shimizu (Kanagawa, JP); Katsumi Suemitsu (Yamagata, JP)
Assignee: Sony Semiconductor Solutions Corporation
H10F39/809H10F39/805H10F39/811
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Quick Facts
Patent No.
US 12,677,497
App. No.
17/259,949
Filed
Jan 13, 2021
Granted
Jul 7, 2026
Kind
B2
Art Unit
2898
USPC
257/292
Abstract

There is provided a semiconductor device having a configuration suitable for higher integration. The semiconductor device includes: a first substrate having a first front surface; and a second substrate having a second front surface joined to the first front surface. The first substrate includes a first wiring layer including a first wiring line, and a first semiconductor layer that are stacked in order from a position close to the second substrate, and the second substrate includes a storage element layer including a storage element, and a second semiconductor layer that are stacked in order from a position close to the first substrate.

Claims (62)

1 . A semiconductor device, comprising:

a first substrate having a first front surface; and

a second substrate having a second front surface joined to the first front surface,

wherein the first substrate includes:

a first wiring layer and a first semiconductor layer that are stacked in order from a position close to the second substrate,

wherein the first wiring layer includes a first wiring line,

wherein the second substrate includes:

a storage element layer and a second semiconductor layer that are stacked in order from a position close to the first substrate,

wherein the storage element layer includes a storage element;

a transistor;

a first contact layer in contact with the storage element;

a second contact layer that couples the storage element and the second substrate to each other;

a protective film covering an end surface of the storage element; and

a hydrogen block layer covering at least a portion of an outer surface of the protective film,

wherein the storage element is sandwiched between the first contact layer and the second contact layer in a stacking direction of the first substrate and the second substrate.

2 . The semiconductor device according to claim 1 , wherein

the first substrate includes a first electrode that is exposed to the first front surface, and

the second substrate includes a second electrode that is exposed to the first front surface and is joined to the first electrode.

3 . The semiconductor device according to claim 1 , wherein the second substrate further includes a second wiring layer located on a side opposite to the second semiconductor layer as viewed from the storage element layer, the second wiring layer including a second wiring line.

4 . The semiconductor device according to claim 1 , wherein the second substrate further includes:

a first terminal provided between the first contact layer and the storage element; and

a second terminal provided between the second contact layer and the storage element,

wherein a thickness of the second terminal is larger than a thickness of the first terminal.

5 . The semiconductor device according to claim 4 , wherein the second terminal includes titanium.

6 . The semiconductor device according to claim 4 , wherein a dimension in an in-plane direction of the second terminal is larger than a dimension in the in-plane direction of the storage element.

7 . The semiconductor device according to claim 1 , wherein the hydrogen block layer includes titanium.

8 . The semiconductor device according to claim 7 , wherein the second contact layer is covered with a titanium-containing layer coupled to the hydrogen block layer.

9 . The semiconductor device according to claim 1 , wherein the first substrate further includes an imaging element provided on a side opposite to the first wiring layer as viewed from the first semiconductor layer.

10 . The semiconductor device according to claim 9 , wherein

the first substrate includes a first electrode that is exposed to the first front surface, and

the second substrate includes a second electrode that is exposed to the first front surface and is joined to the first electrode.

11 . The semiconductor device according to claim 10 , wherein

the first substrate includes a pixel region in which a plurality of the imaging elements is arranged, and a peripheral region surrounding the pixel region, and

a joint section between the first electrode and the second electrode is formed at a position overlapping the pixel region in a stacking direction of the first substrate and the second substrate.

12 . The semiconductor device according to claim 1 , further comprising a third substrate that is provided on a side opposite to the first substrate as viewed from the second substrate, and has a third front surface joined to a second rear surface on a side opposite to the second front surface in the second substrate.

13 . The semiconductor device according to claim 1 , further comprising a third substrate that is provided on a side opposite to the second substrate as viewed from the first substrate, and has a third front surface joined to a first rear surface on a side opposite to the first front surface in the first substrate.

14 . The semiconductor device according to claim 1 , wherein the second substrate further includes a hydrogen block layer between the storage element and the second front surface.

15 . An electronic apparatus, comprising:

an optical system;

a semiconductor device that receives light from the optical system, the semiconductor device including:

a first substrate having a first front surface; and

a second substrate having a second front surface joined to the first front surface,

wherein the first substrate includes:

a first wiring layer and a first semiconductor layer that are stacked in order from a position close to the second substrate,

wherein the first wiring layer includes a first wiring line,

wherein the second substrate includes:

a storage element layer and a second semiconductor layer that are stacked in order from a position close to the first substrate,

wherein the storage element layer includes a storage element;

a transistor;

a first contact layer in contact with the storage element;

a second contact layer that couples the storage element and the second substrate to each other;

a protective film covering an end surface of the storage element; and

a hydrogen block layer covering at least a portion of an outer surface of the protective film,

wherein the storage element is sandwiched between the first contact layer and the second contact layer in a stacking direction of the first substrate and the second substrate; and

a signal processor that processes signals received from the semiconductor device.

16 . The electronic apparatus according to claim 15 , wherein the second substrate further includes a second wiring layer located on a side opposite to the second semiconductor layer as viewed from the storage element layer, the second wiring layer including a second wiring line.

17 . The electronic apparatus according to claim 15 , wherein

the first substrate includes a first electrode that is exposed to the first front surface, and

the second substrate includes a second electrode that is exposed to the first front surface and is joined to the first electrode.

18 . The electronic apparatus according to claim 15 , wherein the first substrate further includes an imaging element provided on a side opposite to the first wiring layer as viewed from the first semiconductor layer.

19 . The electronic apparatus according to claim 15 , further comprising a third substrate that is provided on a side opposite to the first substrate as viewed from the second substrate, and has a third front surface joined to a second rear surface on a side opposite to the second front surface in the second substrate.

20 . The electronic apparatus according to claim 15 , further comprising a third substrate that is provided on a side opposite to the second substrate as viewed from the first substrate, and has a third front surface joined to a first rear surface on a side opposite to the first front surface in the first substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2026
From: SHIMIZU, KAN; SUEMITSU, KATSUMI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 074814/0281 →
Priority Claims (1)
JP 2018-138609 · Jul 24, 2018 · national
Continuity (1)
Related Publication 20210273002A1 · Sep 2, 2021
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