IP Library Granted Patent US 11,687,498
Granted Patent B2
US 11,687,498 · App. 17/302,845 · Granted Jun 27, 2023

Storage appliance for processing of functions as a service (FaaS)

Inventors: Sanjeev N. Trika (Portland, OR); Jawad B. Khan (Portland, OR); Piotr Wysocki (Gdansk, PL)
Assignee: Intel Corporation
G06F16/1834H04L67/104H04L67/34H04L67/01
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Quick Facts
Patent No.
US 11,687,498
App. No.
17/302,845
Granted
Jun 27, 2023
Kind
B2
Abstract

Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.

Claims (34)

1. A storage device comprising:

a computational storage function (CSF) library capable of being stored at the storage device;

a plurality of computational storage engines (CSEs) that are programmable to execute one or more CSFs included in the CSF library, wherein the plurality of CSEs are configurable slots of a field programmable gate array (FPGA); and

control circuitry capable to:

cause a first CSE from among the plurality of CSEs to be programmed to execute a first CSF included in the CSF library, execution of the first CSF to include use of first input data stored at the storage device to generate first output data; and

cause a second CSE from among the plurality of CSEs to be programmed to execute a second CSF included in the CSF library, execution of the second CSF to include use of the first output data to generate second output data.

2. The storage device of claim 1 , further comprising the control circuitry capable to:

cause the second output data to be stored in a mass storage at the storage device.

3. The storage device of claim 1 , comprising the first CSF and the second CSF included in a pipeline CSF, wherein the first CSF and the second CSF are different CSFs.

4. The storage device of claim 3 , wherein the first CSF is an encryption CSF to decrypt the first input data and the second CSF is a compression CSF to decompress the first output data.

5. At least one non-transitory computer-readable medium, comprising instructions that when executed by control circuitry of a storage device, cause the control circuitry to:

cause a first computational storage engine (CSE) at the storage device to execute a first computational storage function (CSF) included in a CSF library stored at the storage device, execution of the first CSF to include use of first input data stored at the storage device to generate first output data; and

cause a second CSE to execute a second CSF included in the CSF library, execution of the second CSF to include use of the first output data to generate second output data, wherein the first CSE is a first configurable slot of a field programmable gate array (FPGA) and the second CSE is a second configurable slot of the FPGA.

6. The at least one non-transitory computer-readable medium of claim 5 , further comprising the instructions to cause the control circuitry to:

cause the second output data to be stored in a mass storage at the storage device.

7. The at least one non-transitory computer-readable medium of claim 5 , comprising the first CSF and the second CSF included in a pipeline CSF, wherein the first CSF and the second CSF are different CSFs.

8. The at least one non-transitory computer-readable medium of claim 7 , wherein the first CSF is a compression CSF to compress the first input data and the second CSF is an encryption CSF to encrypt the first output data.

9. A method comprising:

causing a first computational storage engine (CSE) at a storage device to execute a first computational storage function (CSF) included in a CSF library stored at the storage device, execution of the first CSF to include use of first input data stored at the storage device to generate first output data; and

causing a second CSE to execute a second CSF included in the CSF library, execution of the second CSF to include use of the first output data to generate second output data, wherein the first CSE is a first configurable slot of a field programmable gate array (FPGA) and the second CSE is a second configurable slot of the.

10. The method of claim 9 , further comprising:

causing the second output data to be stored in a mass storage at the storage device.

11. The method of claim 9 , comprising the first CSF and the second CSF included in a pipeline CSF, wherein the first CSF and the second CSF are different CSFs.

12. The method of claim 11 , wherein the first CSF is an encryption CSF to decrypt the first input data and the second CSF is a compression CSF to decompress the first output data.

13. A storage device comprising:

a mass storage to include a solid-state drive; and

a computational storage function (CSF) library capable of being stored at the storage device;

a plurality of computational storage engines (CSEs) that are programmable to execute one or more CSFs included in the CSF library, wherein the plurality of CSEs are configurable slots of a field programmable gate array (FPGA); and

control circuitry capable to:

cause a first CSE from among the plurality of CSEs to be programmed to execute a first CSF included in the CSF library, execution of the first CSF to include use of first input data stored at the storage device to generate first output data; and

cause a second CSE from among the plurality of CSEs to be programmed to execute a second CSF included in the CSF library, execution of the second CSF to include use of the first output data to generate second output data; and

cause the second output data to be stored in the mass storage.

14. The storage device of claim 13 , comprising the first CSF and the second CSF included in a pipeline CSF, wherein the first CSF and the second CSF are different CSFs.

15. The storage device of claim 14 , wherein the first CSF is an encryption CSF to decrypt the first input data and the second CSF is a compression CSF to decompress the first output data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072549/0402 →
Continuity (3)
Continuation 16773826 · Jan 27, 2020
Continuation 16001398 · Jun 6, 2018
Related Publication 20210263895A1 · Aug 26, 2021
Cited By (12)
US 12,189,971 US 12,229,425 US 12,265,719 US 12,271,740 US 12,299,307 US 12,299,460 US 12,333,172 US 12,360,802 US 12,393,432 US 12,399,639 US 12,423,117 US 12,443,436