Multi-gate device and related methods
A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.
1 . A method of fabricating a semiconductor device, comprising:
performing a two-step recess of a shallow trench isolation (STI) region on opposing sides of each of first and second fins, in respective first and second regions, to expose a first number of semiconductor channel layers of the first fin in the first region and a second number of semiconductor channel layers of the second fin in the second region, wherein the second number of exposed semiconductor channel layers is different than the first number of exposed semiconductor channel layers;
after performing the two-step recess of the STI region, forming a multi-layer dielectric over the STI region adjacent to each of the first and second fins; and
after forming the multi-layer dielectric, forming a first gate structure in the first region and a second gate structure in the second region.
2 . The method of claim 1 , wherein a first step of the two-step recess exposes the first number of semiconductor channel layers of both the first fin in the first region and the second fin in the second region, and wherein a second step of the two-step recess exposes at least one additional semiconductor channel layer of the second fin in the second region to provide the second number of exposed semiconductor channel layers.
3 . The method of claim 1 , wherein at least one semiconductor channel layer of the first fin remains embedded within the STI region of the first region after the two-step recess.
4 . The method of claim 1 , wherein the second number of exposed semiconductor channel layers is greater than the first number of exposed semiconductor channel layers.
5 . The method of claim 1 , wherein the first region includes a core device region, and wherein the second region includes an analog device region or a static random-access memory (SRAM) device region.
6 . The method of claim 1 , wherein the first gate structure corresponds to a first transistor, wherein the second gate structure corresponds to a second transistor, and wherein the first and second transistors both include gate-all-around (GAA) transistors.
7 . The method of claim 1 , wherein the forming the multi-layer dielectric over the STI region includes forming the multi-layer dielectric on opposing sides of each of the first and second fins.
8 . The method of claim 1 , wherein the multi-layer dielectric includes a low-K dielectric layer disposed over the STI region and a high-K dielectric layer disposed over the low-K dielectric layer.
9 . The method of claim 1 , further comprising:
after performing the two-step recess of the STI region and prior to forming the first and second gate structures, etching source/drain regions of the second region to remove first portions of the second number of exposed semiconductor channel layers to form a first trench in the source/drain regions of the second region; and
after etching the source/drain regions of the second region, etching source/drain regions of the first region to remove first portions of the first number of exposed semiconductor channel layers to form a second trench in the source/drain regions of the first region.
10 . The method of claim 9 , further comprising:
after forming the first trench and the second trench, epitaxially growing source/drain features within each of the first and second trenches, wherein the source/drain features grown in the first trench contact second portions of the second number of exposed semiconductor channel layers disposed beneath the second gate structure, and wherein the source/drain features grown in the second trench contact second portions of the first number of exposed semiconductor channel layers disposed beneath the first gate structure.
11 . A method, comprising:
forming a plurality of shallow trench isolation (STI) features interposing a plurality of fins each having a stack of epitaxial layers;
performing a first STI recess process to expose a first number of layers of the stack of epitaxial layers within each of the plurality of fins;
performing a second STI recess process to expose a second number of layers of the stack of epitaxial layers in a first substrate region, wherein the second number layers of the stack of epitaxial layers remains embedded within the STI features in a second substrate region after the second STI recess process; and
after performing the second STI recess process, forming a high-K dielectric/low-K dielectric stack over the STI features and adjacent to the exposed layers in each of the first and second substrate regions.
12 . The method of claim 11 , wherein the first substrate region includes an analog device region or a static random-access memory (SRAM) device region, and wherein the second substrate region includes a core device region.
13 . The method of claim 11 , further comprising:
after performing the second STI recess process, selectively removing a portion of at least some layers of the stack of epitaxial layers exposed by the first and second STI recess processes within each of the first substrate region and the second substrate region to form gaps between adjacent layers of the stack of epitaxial layers.
14 . The method of claim 13 , further comprising:
after selectively removing the portion of the at least some layers of the stack of epitaxial layers, forming a portion of a gate structure within each of the gaps.
15 . The method of claim 11 , wherein the exposed first and second numbers of layers include channel layers associated with a transistor in each of the first and second substrate regions, and wherein a first number of channel layers in the first substrate region is greater than a second number of channel layers in the second substrate region.
16 . The method of claim 15 , wherein the transistor in each of the first and second substrate regions includes a gate-all-around (GAA) transistor.
17 . A method, comprising:
performing a multi-step recess of a shallow trench isolation (STI) region in a first substrate region and a second substrate region to expose a first number of channel layers that extend above the STI region in the first substrate region and a second number of channel layers that extend above the STI region in the second substrate region, wherein the first number of channel layers is different than the second number of channel layers; and
after performing the multi-step recess, forming a bi-layer dielectric adjacent to the first number of channel layers in the first substrate region and adjacent to the second number of channel layers in the second substrate region;
wherein a first top surface of the STI region in the first substrate region and a second top surface of the STI region in the second substrate region are offset from one another.
18 . The method of claim 17 , wherein at least one channel layer in the first substrate region remains embedded within the STI region after performing the multi-step recess.
19 . The method of claim 17 , wherein the bi-layer dielectric includes a high-K dielectric/low-K dielectric stack.
20 . The method of claim 17 , further comprising:
after forming the bi-layer dielectric, forming a first gate structure in the first substrate region and a second gate structure in the second substrate region.