Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
1. A method of forming a semiconductor integrated circuit, the method comprising:
providing a substrate comprising a first semiconductor material;
forming a trench in the substrate;
filling the trench with a second semiconductor material, different from the first semiconductor material, to form a trench-filled substrate;
forming a mandrel above the trench-filled substrate;
forming a first and a second sidewall spacer on opposite sides of the mandrel;
wherein (i) the mandrel and (ii) the first and second sidewall spacers extend in a first direction parallel to the substrate, and
wherein the mandrel lies above a boundary between the first semiconductor material and the second semiconductor material, the boundary also extending in the first direction such that the first sidewall spacer lies above the first semiconductor material and the second sidewall spacer lies above the second semiconductor material;
removing the mandrel;
forming a vertical fin comprising the first semiconductor material in a location corresponding to the first sidewall spacer and a dummy fin comprising the second semiconductor material in a location corresponding to the second sidewall spacer; and
subsequently etching the dummy fin as part of a fin-cut process.
2. The method of claim 1 , wherein:
the first semiconductor material is silicon; and
the second semiconductor material is SiGe.
3. The method of claim 1 , wherein the vertical fin and the dummy fin are formed at the same time using a directional etch.
4. The method of claim 1 , wherein the first semiconductor material and the second semiconductor material have about the same etch rate for a directional etch used to form the vertical fin and the dummy fin.
5. The method of claim 1 , further comprising:
planarizing the trench-filled substrate to obtain a substantially flat surface prior to forming the mandrel above the trench-filled substrate.
6. The method of claim 1 , wherein forming the vertical fin comprising the first semiconductor material in the location corresponding to the first sidewall spacer and the dummy fin comprising the second semiconductor material in the location corresponding to the second sidewall spacer comprises using the first and second sidewall spacers as a mask to etch a fin template layer above the trench-filled substrate.
7. The method of claim 1 , wherein the mandrel comprises amorphous silicon.
8. The method of claim 1 , wherein the mandrel comprises amorphous carbon.
9. The method of claim 1 , wherein etching the dummy fin as part of the fin-cut process comprises using a selective etch.
10. The method of claim 9 , wherein the dummy fin is selectively etched using an etchant comprising HCl.
11. A method of forming a semiconductor integrated circuit, the method comprising:
providing a substrate comprising a first semiconductor material;
forming a first trench in a first portion of the substrate and a second trench in a second portion of the substrate;
filling the first and second trenches with a second semiconductor material, different from the first semiconductor material, to form first and second portions of a trench-filled substrate, wherein the first and second portions are separated by a third portion of the trench-filled substrate comprising the first semiconductor material;
forming a plurality of vertical fins comprising the first semiconductor material in the third portion of the trench-filled substrate;
forming a first dummy fin (i) directly adjacent a first vertical fin and (ii) in the first portion of the trench-filled substrate;
forming a second dummy fin (i) directly adjacent a second vertical fin and (ii) in the second portion of the trench-filled substrate; and
subsequently etching the first and second dummy fins as part of a fin-cut process.
12. The method of claim 11 , wherein:
the first semiconductor material is silicon; and
the second semiconductor material is SiGe.
13. The method of claim 11 , wherein (i) the plurality of vertical fins and (ii) the first and second dummy fins are formed at the same time using a directional etch.
14. The method of claim 11 , wherein the first semiconductor material and the second semiconductor material have about the same etch rate for a directional etch used to form the plurality of vertical fins and the first and second dummy fins.
15. The method of claim 11 , further comprising:
planarizing the trench-filled substrate to obtain a substantially flat surface prior to forming the plurality of vertical fins and the first and second dummy fins.
16. The method of claim 11 , wherein forming the plurality of vertical fins and the first and second dummy fins further comprises using sidewall spacers as a mask to etch a fin template layer above the trench-filled substrate.
17. The method of claim 16 , wherein the sidewall spacers comprise silicon oxide or silicon nitride.
18. The method of claim 16 , wherein the sidewall spacers comprise SiBCN or SiOC.
19. The method of claim 11 , wherein etching the first and second dummy fins as part of the fin-cut process comprises using a selective etch.
20. The method of claim 19 , wherein the first and second dummy fins are selectively etched using an etchant comprising HCl.