Image sensor
An imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.
1. An imaging device comprising:
an image sensor comprising:
a first substrate including a pixel array comprising a plurality of pixels disposed on the first substrate;
a first substrate read bus communicating with at least one of the plurality of pixels on the pixel array;
a plurality of interconnects;
a second substrate including supporting circuitry for the pixel array and a second substrate read bus, the second substrate being in electrical communication with the first substrate by the plurality of interconnects;
wherein at least one interconnect of the plurality of interconnects connects the first substrate read bus to the second substrate read bus, thereby providing electrical communication between the at least one pixel and the supporting circuitry;
wherein the at least one interconnect is located anywhere along a connection between the first substrate read bus and the second substrate read bus.
2. The imaging device of claim 1 , wherein the supporting circuitry includes one or more of an analog to digital converter, a power circuit, a power harvester, an amplifier circuit, a dedicated signal processor, a filter, and a serializer.
3. The imaging device of claim 1 , wherein the interconnects include one or more of a wirebond, a μbump, a solder bump, a solder ball, and a through silicon via.
4. The imaging device of claim 1 , wherein said pixel array includes a plurality of pixel columns arranged into a plurality of pixel sub-columns.
5. The imaging device of claim 4 , wherein a plurality of first substrate read buses are provided on the first substrate, where a first substrate read bus is provided for each one of the plurality of pixel sub-columns on the first substrate.
6. The imaging device of claim 5 , wherein each first substrate read bus provides electrical communication for one of the plurality of pixel sub-columns to the supporting circuitry for the one pixel sub-column on the second substrate via a corresponding second substrate read bus on the second substrate.
7. The imaging device of claim 6 , wherein the plurality of interconnects further connect each first substrate read bus its corresponding second substrate read bus.
8. The imaging device of claim 7 , wherein each interconnect connects to a first substrate read bus at a point along a physical path where the first substrate read bus overlaps the corresponding second substrate read bus at a point along a physical path of the corresponding second substrate read bus.
9. The imaging device of claim 1 , wherein the first substrate includes a surface area that is substantially equivalent to a surface area of the second substrate.
10. The imaging device of claim 1 , wherein the first substrate includes a surface area that is less than the surface area of the second substrate.
11. The imaging device of claim 1 , wherein the first substrate further includes a second pixel array.
12. The imaging device of claim 11 , wherein the second pixel array enables three dimensional image capture.
13. The imaging device of claim 1 , wherein the first substrate and the second substrate are vertically stacked.
14. The imaging device of claim 4 , wherein a first substrate read bus is provided for each two of the plurality of pixel sub-columns on the first substrate.
15. The imaging device of claim 14 , wherein each first substrate read bus includes a select transistor to select which one of the two of the plurality of pixel sub-columns on the first substrate to read.
16. The imaging device of claim 1 , wherein an interconnect is provided for each individual pixel in the pixel array.
17. The imaging device of claim 16 , wherein the interconnect is a bump with a bump pitch that substantially equals a pixel pitch of the pixels in the pixel array in both an X direction and a Y direction of the first substrate and the second substrate.
18. An imaging device comprising:
an image sensor comprising:
a first substrate including a pixel array comprising a plurality of pixels disposed on the first substrate;
a first substrate read bus communicating with at least one of the plurality of pixels on the pixel array, wherein the pixel array is a column of pixels M pixels wide and N pixels long;
a plurality of interconnects; and
a second substrate including supporting circuitry for the pixel array and a second substrate read bus, the second substrate being in electrical communication with the first substrate by the plurality of interconnects;
wherein at least one interconnect of the plurality of interconnects connects the first substrate read bus to the second substrate read bus, thereby providing electrical communication between the at least one pixel and the supporting circuitry;
wherein the at least one interconnect is located anywhere along a connection between the first substrate read bus and the second substrate read bus.
19. The imaging device of claim 18 , wherein the aspect ratio of the pixel array is 1:N.
20. The imaging device of claim 1 , wherein the interconnect connects to the first substrate read bus at a point along a physical path where the first substrate read bus overlaps the second substrate read bus.