Semiconductor device and method of embedding circuit pattern in encapsulant for SIP module
An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.
1. A method of making a semiconductor device, comprising:
providing a semiconductor component assembly including a semiconductor component and an encapsulant disposed over the semiconductor component assembly and semiconductor component;
forming a plurality of openings in a surface of the encapsulant including over at least a portion of the semiconductor component in a form of a circuit pattern;
depositing a conductive material in the openings to form an electrical circuit pattern; and
disposing an electrical component over the electrical circuit pattern.
2. The method of claim 1 , further including:
applying the conductive material over the surface of the encapsulant; and
removing a portion of the conductive material to expose the electrical circuit pattern.
3. The method of claim 1 , further including planarizing the surface of the encapsulant and the electrical circuit pattern.
4. The method of claim 1 , wherein the electrical circuit pattern includes an interconnect structure.
5. The method of claim 1 , wherein the electrical circuit pattern includes a shielding layer.
6. The method of claim 1 , further including forming the plurality of openings in the encapsulant by laser.
7. A method of making a semiconductor device, comprising:
forming a plurality of openings partially into a surface of an encapsulant in a form of a circuit pattern; and
depositing a conductive material in the openings to form an electrical circuit pattern.
8. The method of claim 7 , further including disposing an electrical component over and electrically connected to the electrical circuit pattern.
9. The method of claim 7 , further including:
applying the conductive material over the surface of the encapsulant; and
removing a portion of the conductive material to expose the electrical circuit pattern.
10. The method of claim 7 , further including planarizing the surface of the encapsulant and the electrical circuit pattern.
11. The method of claim 7 , wherein the electrical circuit pattern includes an interconnect structure.
12. The method of claim 7 , wherein the electrical circuit pattern includes a shielding layer.
13. The method of claim 7 , further including forming the plurality of openings in the encapsulant by laser.
14. A semiconductor device, comprising:
a semiconductor component assembly;
an encapsulant disposed over the semiconductor component assembly;
a plurality of openings formed into a surface of the encapsulant in a form of a circuit pattern;
a conductive material deposited in the openings to form an electrical circuit pattern; and
an electrical component disposed over the electrical circuit pattern.
15. The semiconductor device of claim 14 , wherein the conductive material is disposed over the surface of the encapsulant.
16. The semiconductor device of claim 14 , wherein the surface of the encapsulant and the electrical circuit pattern are planarized.
17. The semiconductor device of claim 14 , wherein the electrical circuit pattern includes an interconnect structure.
18. The semiconductor device of claim 14 , wherein the electrical circuit pattern includes a shielding layer.
19. The semiconductor device of claim 14 , further including a laser to form the plurality of openings in the encapsulant.
20. A semiconductor device, comprising:
an encapsulant;
a plurality of openings formed into a surface of the encapsulant in a form of a circuit pattern; and
a conductive material deposited in the openings to form an electrical circuit pattern.
21. The semiconductor device of claim 20 , further including an electrical component disposed over the electrical circuit pattern.
22. The semiconductor device of claim 20 , wherein the conductive material is disposed over the surface of the encapsulant.
23. The semiconductor device of claim 20 , wherein the surface of the encapsulant and the electrical circuit pattern are planarized.
24. The semiconductor device of claim 20 , wherein the electrical circuit pattern includes an interconnect structure or shielding layer.
25. The semiconductor device of claim 20 , further including a laser to form the plurality of openings in the encapsulant.
26. The semiconductor device of claim 20 , further including a semiconductor component, wherein the encapsulant is deposited over the semiconductor component and the openings are formed over at least a portion of the semiconductor component.
27. The method of claim 7 , further including providing a semiconductor component, wherein the encapsulant is deposited over the semiconductor component and the openings are formed over at least a portion of the semiconductor component.
28. The semiconductor device of claim 14 , further including a semiconductor component, wherein the encapsulant is deposited over the semiconductor component and the openings are formed over at least a portion of the semiconductor component.