Output-integrated transistor device packages

1. A semiconductor device package comprising:

a plurality of input leads;

a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads; and

a combined output lead comprising an edge plane that laterally extends between outputs of the plurality of transistor amplifier dies and is configured to output a combined signal from the semiconductor device package.

2. The semiconductor device package of claim 1 , wherein the plurality of transistor amplifier dies are second transistor amplifier dies,

wherein the plurality of input leads are a plurality of second input leads, and

wherein the semiconductor device package further comprises:

a first input lead;

a first output lead separate from the combined output lead; and

a first transistor amplifier die coupled between the first input lead and the first output lead.

3. The semiconductor device package of claim 2 , wherein the first transistor amplifier die is a main amplifier of a Doherty amplifier and the plurality of second transistor amplifier dies are peaking amplifiers of the Doherty amplifier.

4. The semiconductor device package of claim 1 , wherein at least a portion of the combined output lead is within the semiconductor device package.

5. The semiconductor device package of claim 1 , further comprising a plurality of output prematch circuits respectively between ones of the plurality of transistor amplifier dies and the combined output lead.

6. The semiconductor device package of claim 1 , wherein the plurality of input leads are configured to receive a plurality of input signals that are respectively out of phase with one another.

7. The semiconductor device package of claim 1 , further comprising a first output lead that is separate from the combined output lead, wherein:

the first output lead is configured to couple a first transistor amplifier die from among the plurality of transistor amplifier dies to a first output match circuit, and

the combined output lead is configured to couple a plurality of second transistor amplifier dies from among the plurality of transistor amplifier dies to a second output match circuit.

8. A semiconductor package comprising:

a plurality of input leads;

a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads; and

a combined output lead configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal, wherein the combined output lead comprises an internal portion that is within the semiconductor device package and a protrusion that extends from the internal portion out of the semiconductor device package.

9. The semiconductor device package of claim 8 , wherein the protrusion is a first protrusion, and

wherein the combined output lead comprises a second protrusion, separated from the first protrusion, that extends from the internal portion of the combined output lead out of the semiconductor device package.

10. A semiconductor package comprising:

a plurality of input leads;

a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads; and

a combined output lead configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal, wherein a width of the combined output lead extends from a portion of an interior of the semiconductor device package that is adjacent a first of the plurality of transistor amplifier dies to a portion of the interior of the semiconductor device package that is adjacent a second of the plurality of transistor amplifier dies.

11. A semiconductor package comprising:

a plurality of input leads;

a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads; and

a combined output lead configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal, wherein the combined output lead extends to at least partially overlap each of the plurality of transistor amplifier dies.

12. A semiconductor device package comprising:

a first transistor amplifier die coupled to a first input lead of the semiconductor device package;

a plurality of second transistor amplifier dies respectively coupled to a plurality of second input leads of the semiconductor device package; and

a combined output lead that is configured to output a combination of output signals of respective ones of the plurality of second transistor amplifier dies,

wherein the combined output lead comprises an internal portion that is within the semiconductor device package and extends along the plurality of second transistor amplifier dies.

13. The semiconductor device package of claim 12 , wherein the semiconductor device package is a Doherty amplifier package,

wherein the plurality of second transistor amplifier dies comprise a first peaking transistor amplifier and a second peaking transistor amplifier of the Doherty amplifier package, and

wherein the first transistor amplifier die comprises a main amplifier of the Doherty amplifier package.

14. The semiconductor device package of claim 12 , wherein the combined output lead is further configured to combine the output of the first transistor amplifier die with the combination of the output of the plurality of second transistor amplifier dies.

15. The semiconductor device package of claim 12 , wherein the combined output lead comprises a first output lead and a second output lead electrically coupled together.

16. The semiconductor device package of claim 15 , wherein the first output lead and the second output lead are electrically coupled together by bond wires.

17. The semiconductor device package of claim 12 , wherein the combined output lead further comprises a protrusion that extends from the internal portion out of the semiconductor device package.

18. The semiconductor device package of claim 12 , further comprising an output prematch circuit between respective ones of the plurality of second transistor amplifier dies and the combined output lead.

19. A semiconductor device package comprising:

a plurality of transistor amplifier dies, each respectively coupled to one of a plurality of input leads of the semiconductor device package; and

a combined output lead configured to combine output signals from two or more of the plurality of transistor amplifier dies to generate a combined output signal that is provided as an output of the semiconductor device package,

wherein the combined output lead extends to at least partially overlap the two or more of the plurality of transistor amplifier dies.

20. The semiconductor device package of claim 19 , further comprising a plurality of output prematch circuits respectively between ones of the plurality of transistor amplifier dies and the combined output lead.

21. The semiconductor device package of claim 19 , wherein the plurality of transistor amplifier dies are second transistor amplifier dies,

wherein the plurality of input leads are a plurality of second input leads, and

wherein the semiconductor device package further comprises:

a first input lead;

a first output lead separate from the combined output lead; and

a first transistor amplifier die coupled between the first input lead and the first output lead.

22. The semiconductor device package of claim 21 , wherein the first transistor amplifier die is a main amplifier of a Doherty amplifier and the plurality of second transistor amplifier dies are peaking amplifiers of the Doherty amplifier.

23. The semiconductor device package of claim 21 , wherein the combined output lead is further configured to combine the output signals from the two or more of the plurality of second transistor amplifier dies with an output signal of the first transistor amplifier die to generate the combined output signal.