Integrated circuit package and method

1. A method comprising:

bonding a first integrated circuit device and a second integrated circuit device to a front side of an interposer;

adhering a plurality of heat dissipation dies in a stack on the first integrated circuit device, the heat dissipation dies comprising an upper heat dissipation die;

encapsulating the heat dissipation dies, the first integrated circuit device, and the second integrated circuit device with an encapsulant;

thinning the encapsulant, the upper heat dissipation die, and the second integrated circuit device until a top surface of the encapsulant is coplanar with a top surface of the upper heat dissipation die and a top surface of the second integrated circuit device; and

adhering a heat spreader to the top surface of the encapsulant, the top surface of the upper heat dissipation die, and the top surface of the second integrated circuit device.

2. The method of claim 1 , wherein a first portion of the encapsulant covers the top surface of the upper heat dissipation die, and thinning the encapsulant removes the first portion of the encapsulant.

3. The method of claim 1 , wherein the top surface of the second integrated circuit device is disposed further from the interposer than the top surface of the first integrated circuit device, the top surface of the upper heat dissipation die is disposed further from the interposer than the top surface of the second integrated circuit device before thinning the upper heat dissipation die, and the top surface of the upper heat dissipation die is disposed the same distance from the interposer as the top surface of the second integrated circuit device after thinning the upper heat dissipation die.

4. The method of claim 1 , wherein the second integrated circuit device is a high bandwidth memory (HBM) device.

5. The method of claim 1 , wherein the first integrated circuit device is a system-on-integrated-chip (SoIC) device.

6. The method of claim 1 , wherein the first integrated circuit device is an integrated circuit die.

7. The method of claim 1 , wherein a width of the heat dissipation dies equals a width of the first integrated circuit device.

8. The method of claim 1 , wherein a width of the heat dissipation dies is greater than a width of the first integrated circuit device.

9. The method of claim 1 , wherein a width of the heat dissipation dies is less than a width of the first integrated circuit device.

10. A method comprising:

bonding a first die stack and a second die stack to a front side of an interposer;

adhering a plurality of heat dissipation dies in a stack on the first die stack, the heat dissipation dies comprising an upper heat dissipation die;

encapsulating the heat dissipation dies, the first die stack, and the second die stack with a first encapsulant;

thinning the first encapsulant and the upper heat dissipation die until a top surface of the first encapsulant is coplanar with a top surface of the upper heat dissipation die and a top surface of the second die stack; and

adhering a heat spreader to the top surface of the first encapsulant, the top surface of the upper heat dissipation die, and the top surface of the second die stack.

11. The method of claim 10 , wherein the top surface of the second die stack is disposed further from the interposer than the top surface of the first die stack, the top surface of the upper heat dissipation die is disposed further from the interposer than the top surface of the second die stack before thinning the upper heat dissipation die, and the top surface of the upper heat dissipation die is disposed the same distance from the interposer as the top surface of the second die stack after thinning the upper heat dissipation die.

12. The method of claim 10 , further comprising forming the second die stack by:

bonding a first integrated circuit die to a second integrated circuit die, the first integrated circuit die comprising first conductive vias;

encapsulating the first integrated circuit die with a second encapsulant; and

forming a redistribution structure on the second encapsulant and the first integrated circuit die, the redistribution structure connected to the first conductive vias.

13. The method of claim 10 , further comprising forming the second die stack by:

bonding a first integrated circuit die to a second integrated circuit die, the first integrated circuit die comprising first conductive vias;

encapsulating the second integrated circuit die with a second encapsulant; and

forming a redistribution structure on the first integrated circuit die, the redistribution structure connected to the first conductive vias.

14. The method of claim 10 , wherein a width of the heat dissipation dies equals a width of the first die stack.

15. The method of claim 10 , wherein a width of the heat dissipation dies is greater than a width of the first die stack.

16. The method of claim 10 , wherein a width of the heat dissipation dies is less than a width of the first die stack.

17. A method comprising:

bonding a logic device and a memory device to a front side of an interposer;

adhering a heat dissipation die stack on the logic device, the heat dissipation die stack comprising an upper heat dissipation die and a lower heat dissipation die, the upper heat dissipation die and the lower heat dissipation die each having a greater width than the logic device;

encapsulating the heat dissipation die stack, the logic device, and the memory device with an encapsulant;

thinning the encapsulant and the upper heat dissipation die until a top surface of the encapsulant is coplanar with a top surface of the upper heat dissipation die and a top surface of the memory device, the upper heat dissipation die having a lesser thickness than the lower heat dissipation die after thinning the upper heat dissipation die; and

adhering a heat spreader to the top surface of the encapsulant, the top surface of the upper heat dissipation die, and the top surface of the memory device.

18. The method of claim 17 , wherein the logic device is a system-on-integrated-chip (SoIC) device and the memory device is a high bandwidth memory (HBM) device.

19. The method of claim 17 , wherein a first portion of the encapsulant covers the top surface of the upper heat dissipation die, and thinning the encapsulant removes the first portion of the encapsulant.

20. The method of claim 17 , wherein the top surface of the memory device is disposed further from the interposer than the top surface of the logic device, the top surface of the upper heat dissipation die is disposed further from the interposer than the top surface of the memory device before thinning the upper heat dissipation die, and the top surface of the upper heat dissipation die is disposed the same distance from the interposer as the top surface of the memory device after thinning the upper heat dissipation die.