IP Library Granted Patent US 11,487,684
Granted Patent B2
US 11,487,684 · App. 17/315,267 · Granted Nov 1, 2022

Power management in a seamlessly integrated microcontroller chip

Inventor: Scott David Kee (Aliso Viejo, CA)
Assignee: AyDeeKay LLC
G06F13/26G06F3/0659G06F3/0679G06F12/0638G06F12/0866G06F13/14G06F13/1668G06F13/28G06F13/364G06F13/4027G06F13/4068G06F13/4282G06F21/76G06F2213/0062G06F2213/40G06F2221/2103
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Quick Facts
Patent No.
US 11,487,684
App. No.
17/315,267
Granted
Nov 1, 2022
Kind
B2
Abstract

A system that includes a first die with a central processing unit (CPU) and a second die electrically coupled to the first die by die-to-die interconnects is described. During operation, the first die: provides, to the second die, a set of predefined wake-up events; provides, to the second die, a message that transitions power-management control of the first die to the second die; and transitions the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode. Then, the second die: determines an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and provides, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.

Claims (49)

1. A system, comprising:

a first die with a central processing unit (CPU); and

a second die electrically coupled to the first die by die-to-die interconnects, wherein the first die is configured to:

provide, to the second die, a set of predefined wake-up events;

provide, to the second die, a message that transitions power-management control of the first die to the second die; and

transition the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode; and

wherein the second die is configured to:

determine an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and

provide, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.

2. The system of claim 1 , wherein the second die comprises an ASIC die.

3. The system of claim 1 , wherein, in the second operating mode, control logic and memory in the first die are powered off.

4. The system of claim 3 , wherein the control logic comprises a direct memory access (DMA) controller.

5. The system of claim 1 , wherein the information transitions power-management control of the first die back to the first die.

6. The system of claim 1 , wherein the information is provided to a core of the CPU.

7. The system of claim 1 , wherein, in the first operating mode, the first die and the second die are configured to operate power-management units, and operation of the power-management units is coordinated asynchronously between the first die and the second die.

8. The system of claim 7 , wherein the coordination comprises synchronization of state machines associated with the power-management units in the first die and the second die.

9. The system of claim 1 , wherein the set of predefined wake-up events is programmable.

10. The system of claim 1 , wherein the determining comprises translating an interrupt to the predefined wake-up event and the information specifies the predefined wake-up event; and

wherein, after the first die receives the information, the first die is configured to translate the information to the interrupt.

11. The system of claim 10 , wherein the communication via the die-to-die interconnects and the translation of the information to the interrupt enable the CPU to operate as if the interrupt occurred in a single-die system.

12. The system of claim 1 , wherein the predefined wake-up event comprises an interrupt; and

wherein the second die is configured to:

hold the interrupt until the first die transitions to the first operating mode; and

provide, to the first die, the interrupt.

13. The system of claim 12 , wherein the second die is configured to hold the interrupt until the first die transitions to the first operating mode when a debug port on the second die is active.

14. The system of claim 1 , wherein transitioning to the first operating mode comprises powering on and booting the CPU.

15. The system of claim 1 , wherein the information specifies the determined predefined wake-up event.

16. The system of claim 1 , wherein the second die comprises a debug port that is configured to facilitate debugging of the CPU from the second die.

17. A method of performing power management, comprising:

providing, from a first die with a central processing unit (CPU) to a second die that is electrically coupled to the first die by die-to-die interconnects, a set of predefined wake-up events;

providing, from the first die to the second die, a message that transitions power-management control of the first die to the second die;

transitioning the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode;

determining, by the second die, an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and

providing, from the second die to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.

18. The method of claim 17 , wherein the determining comprises translating an interrupt to the predefined wake-up event and the information specifies the predefined wake-up event; and

wherein, after the first die receives the information, translating, by the first die, the information to the interrupt.

19. The method of claim 17 , wherein the predefined wake-up event comprises an interrupt; and

wherein the method comprises:

holding, at the second die, the interrupt until the first die transitions to the first operating mode; and

provide, from the second die to the first die, the interrupt.

20. An electronic device, comprising:

a first die with a central processing unit (CPU); and

a second die electrically coupled to the first die by die-to-die interconnects, wherein the first die is configured to:

provide, to the second die, a set of predefined wake-up events;

provide, to the second die, a message that transitions power-management control of the first die to the second die; and

transition the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode; and

wherein the second die is configured to:

determine an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and

provide, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2021
From: KEE, SCOTT DAVID
To: AYDEEKAY LLC DBA INDIE SEMICONDUCTOR
Reel/Frame 056181/0717 →
Continuity (3)
Continuation 17225057 · Apr 7, 2021
Provisional Application 63010341 · Apr 15, 2020
Related Publication 20210326073A1 · Oct 21, 2021
Cited By (1)
US 12,609,697