Phase skipping technique for high-speed, high-phase number delay locked loop
A delay locked loop (DLL) circuit includes inputs from M-phase clocks, M is an integer that is greater than or equal to 1; N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*Δt, N is an integer, and k is an integer that is coprime with both N and M; N outputs for clock phases from the N delay cells; and an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.
1. A delay locked loop (DLL) circuit comprising:
inputs from M-phase clocks, M is an integer that is greater than or equal to 2, wherein clock phases for the M-phase clocks are each 2*pi/M radians apart;
N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*Δt, N is an integer, and k is an integer that is coprime with both N and M;
N outputs for clock phases from the N delay cells; and
an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.
2. The DLL circuit of claim 1 , wherein Δt=1/(F*N) where F is a frequency of the M-phase clocks.
3. The DLL circuit of claim 2 , wherein a total delay of each of the M separate delay lines is (k/M)*(1/F).
4. The DLL circuit of claim 1 , wherein N is even and k is odd.
5. The DLL circuit of claim 1 , wherein each of the N delay cells includes an inverter.
6. The DLL circuit of claim 1 , wherein outputs of consecutive delay cells in each of the M separate delay lines are not adjacent clock phases.
7. The DLL circuit of claim 6 , wherein, for each of the M separate delay lines, missing clock phases between the consecutive delay cells are generated at subsequent points from the consecutive delay cells.
8. The DLL circuit of claim 1 , further comprising
a clock generation circuit connected to each of the N outputs to provide retimed output clocks for each of the M separate delay lines.
9. A method comprising:
receiving inputs from M-phase clocks, M is an integer that is greater than or equal 2, wherein clock phases for the M-phase clocks are each 2*pi/M radians apart;
operating N delay cells in each of M separate delay lines connected to the inputs, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*Δt, N is an integer, and k is an integer that is coprime with both N and M;
providing N outputs for clock phases from the N delay cells; and
locking the N delay cells utilizing an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks.
10. The method of claim 9 , wherein Δt=1/(F*N) where F is a frequency of the M-phase clocks.
11. The method of claim 10 , wherein a total delay of each of the M separate delay lines is (k/M)*(1/F).
12. The method of claim 9 , wherein N is even and k is odd.
13. The method of claim 9 , wherein each of the N delay cells includes an inverter.
14. The method of claim 9 , wherein outputs of consecutive delay cells in each of the M separate delay lines are not adjacent clock phases.
15. The method of claim 14 , wherein, for each of the M separate delay lines, missing clock phases between the consecutive delay cells are generated at subsequent points from the consecutive delay cells.
16. The method of claim 9 , further comprising
utilizing a clock generation circuit connected to each of the N outputs for the inputs to provide retimed output clocks for each of the M separate delay lines.