Fabricating field-effect transistors with interleaved source and drain finger configuration
The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.
1. A method for fabricating a field-effect transistor (FET), the method comprising:
providing a substrate;
implementing a first assembly of source, gate, and drain on a first active region of the substrate;
implementing a second assembly of source, gate, and drain implemented on a second active region of the substrate;
implementing a third assembly of source, gate, and drain on a third active region of the substrate;
forming a first body contact between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly;
forming a second body contact between the second assembly and the third assembly, the first assembly and the third assembly being dimensioned the same such that the first body contact and the second body contact are positioned symmetrically about a center line of the FET, the second assembly being dimensioned such that it has a width that is equal to the combined widths of the first assembly and the third assembly;
forming a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers, the finger configuration of each of the first assembly and the second assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows; and
electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is positioned on the same row as the particular source finger of the first assembly.
2. The method of claim 1 wherein the substrate includes a silicon-on-insulator (SOI) substrate.
3. The method of claim 1 wherein the first assembly and the second assembly are dimensioned the same and the first body contact is positioned at the center of the FET.
4. The method of claim 1 further comprising electrically connecting a particular drain finger of the first assembly to a drain finger of the second assembly that is positioned on the same row as the particular drain finger of the first assembly.
5. The method of claim 1 further comprising forming a finger configuration for the source, the gate, and the drain on the third assembly, each finger configuration including a plurality of fingers, the finger configuration of the third assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows.
6. The method of claim 5 further comprising electrically connecting the gate fingers of each of the first assembly, the second assembly, and the third assembly.
7. A method for fabricating a field-effect transistor (FET), the method comprising:
providing a substrate;
implementing a first assembly of source, gate, and drain on a first active region of the substrate;
implementing a second assembly of source, gate, and drain implemented on a second active region of the substrate;
implementing a third assembly of source, gate, and drain on a third active region of the substrate;
forming a first body contact between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly;
forming a second body contact between the second assembly and the third assembly, the first assembly and the third assembly being dimensioned the same such that the first body contact and the second body contact are positioned symmetrically about a center line of the FET, the second assembly being dimensioned such that it has a width that is equal to the combined widths of the first assembly and the third assembly;
forming a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers, the finger configuration of each of the first assembly and the second assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows; and
electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is offset by one row from the particular source finger of the first assembly.
8. The method of claim 7 wherein the substrate includes a silicon-on-insulator (SOI) substrate.
9. The method of claim 7 wherein the first assembly and the second assembly are dimensioned the same and the first body contact is positioned at the center of the FET.
10. The method of claim 7 further comprising electrically connecting a particular drain finger of the first assembly to a drain finger of the second assembly that is offset by one row from the particular drain finger of the first assembly.
11. The method of claim 7 further comprising forming a finger configuration for the source, the gate, and the drain on the third assembly, each finger configuration including a plurality of fingers, the finger configuration of the third assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows.
12. The method of claim 11 further comprising electrically connecting the gate fingers of each of the first assembly, the second assembly, and the third assembly.
13. A method for fabricating a radio-frequency (RF) device, the method comprising:
forming a field-effect transistor (FET) over a substrate layer, the FET including a first assembly of source, gate, and drain on a first active region of the substrate layer, the FET also including a second assembly of source, gate, and drain implemented on a second active region of the substrate layer, the FET also including a third assembly of source, gate, and drain implemented on a third active region of the substrate layer, the FET also including a first body contact implemented between the first assembly and the second assembly, the first body contact formed such that application of a voltage on the first body contact influences operation of the first assembly and the second assembly, the FET also including a second body contact implemented between the second assembly and the third assembly, the first assembly and the third assembly being dimensioned the same such that the first body contact and the second body contact are positioned symmetrically about a center line of the FET, the second assembly being dimensioned such that it has a width that is equal to the combined widths of the first assembly and the third assembly, the FET also including a finger configuration for the source, the gate, and the drain on each of the first assembly and the second assembly, each finger configuration including a plurality of fingers, the finger configuration of each of the first assembly and the second assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows;
electrically connecting a particular source finger of the first assembly to a source finger of the second assembly that is positioned on the same row or that is offset by one row from the particular source finger of the first assembly;
electrically connecting the substrate layer to a substrate node; and
coupling a non-grounding circuit to the substrate node to adjust RF performance of the FET.
14. The method of claim 13 wherein the RF device is a switch.
15. The method of claim 13 wherein the substrate includes a silicon-on-insulator (SOI) substrate.
16. The method of claim 13 wherein the first assembly and the second assembly are dimensioned the same and the first body contact is positioned at the center of the FET.
17. The method of claim 13 further comprising electrically connecting a particular drain finger of the first assembly to a drain finger of the second assembly that is offset by one row from the particular drain finger of the first assembly.
18. The method of claim 13 further comprising electrically connecting a particular drain finger of the first assembly to a drain finger of the second assembly that is positioned on the same row as the particular drain finger of the first assembly.
19. The method of claim 13 , wherein the FET also includes a finger configuration for the source, the gate, and the drain on the third assembly, each finger configuration including a plurality of fingers, the finger configuration of the third assembly resulting in source fingers and drain fingers being interleaved with the gate fingers, the source fingers and the drain fingers arranged in alternating rows.
20. The method of claim 19 further comprising electrically connecting the gate fingers of each of the first assembly, the second assembly, and the third assembly.