Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers
A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.
1. A semiconductor device, comprising:
a substrate;
two source/drain features over the substrate;
channel layers connecting the two source/drain features; and
a gate structure wrapping around each of the channel layers,
wherein each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer,
wherein the channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers,
wherein the first epitaxial layers include a first semiconductor material with a first dopant species, the second epitaxial layers include the first semiconductor material with a second dopant species different from the first dopant species, and
wherein a charge carrier has a first mobility in the first semiconductor material with the first dopant species and a second mobility in the first semiconductor material with the second dopant species, wherein the first mobility is lower than the second mobility.
2. The semiconductor device of claim 1 , wherein a top surface of the first epitaxial layers extends along a top surface of the substrate.
3. The semiconductor device of claim 1 , wherein the first semiconductor material is silicon, the first dopant species is carbon, and the second dopant species is an n-type dopant.
4. The semiconductor device of claim 1 , wherein the first semiconductor material is silicon and the second dopant species is arsenic.
5. The semiconductor device of claim 1 , wherein the third epitaxial layers include the first semiconductor material with a third dopant species, and the third dopant species is different from the first dopant species and the second dopant species.
6. The semiconductor device of claim 5 , wherein the second dopant species and the third dopant species are both n-type dopants.
7. The semiconductor device of claim 6 , wherein the charge carrier has a third mobility in the first semiconductor material with the third dopant species, and the second mobility is less than the third mobility.
8. The semiconductor device of claim 7 , wherein an atomic percentage of the first dopant species in the first epitaxial layers is about 10% to about 30%, an atomic percentage of the second dopant species in the second epitaxial layers is about 10% to about 30%, and an atomic percentage of the third dopant species in the third epitaxial layers is about 30% to about 80%.
9. The semiconductor device of claim 1 , further comprising a silicide layer, the silicide layer having a bottom surface interfaced with the third epitaxial layers and sidewall surfaces interfaced with the second epitaxial layers, wherein the silicide layer is spaced away from the first epitaxial layers.
10. The semiconductor device of claim 1 , wherein the third epitaxial layer has a bottom surface that extends below a bottom surface of a lowest layer of the channel layers.
11. The semiconductor device of claim 10 , wherein the second epitaxial layer has a sidewall surface that includes a plurality of “S”-shaped segments.
12. A semiconductor device, comprising:
a substrate;
two source/drain features over the substrate; and
suspended channel layers connecting the two source/drain features,
wherein each of the source/drain features include a first epitaxial layer, a second epitaxial layer on sidewalls of the first epitaxial layer, and a third epitaxial layer below the first and the second epitaxial layers and below a lowest layer of the suspended channel layers,
wherein the first epitaxial layer includes a first dopant species, the second epitaxial layer includes a second dopant species, and the third epitaxial layer includes a third dopant species, and wherein the first dopant species, the second dopant species, and the third dopant species are different, and
wherein each of the suspended channel layers directly interface with the first epitaxial layer of the source/drain features.
13. The semiconductor device of claim 12 , wherein the first epitaxial layers each interpose between the suspended channel layers and one of the second epitaxial layers.
14. The semiconductor device of claim 12 , wherein the second epitaxial layer is spaced away from the third epitaxial layer.
15. The semiconductor device of claim 12 , wherein the third dopant species is carbon.
16. The semiconductor device of claim 12 , wherein the first dopant species is arsenic, and the second dopant species is phosphorous.
17. A method, comprising:
receiving a semiconductor structure having a semiconductor channel over a substrate and source/drain trenches in the substrate and on both sides of the semiconductor channel;
epitaxially growing first epitaxial layers in the source/drain trenches, wherein the first epitaxial layers are below a bottom surface of the semiconductor channel, and wherein the first epitaxial layers include a first dopant;
epitaxially growing second epitaxial layers on the first epitaxial layers and on sidewalls surfaces of the source/drain trenches, wherein the second epitaxial layers are connected to the semiconductor channel and include a second dopant; and
epitaxially growing third epitaxial layers on the second epitaxial layers, wherein the third epitaxial layers include a third dopant and the second epitaxial layers are between the third epitaxial layers and the semiconductor channel,
wherein the first dopant is different from the second dopant and the third dopant in species.
18. The method of claim 17 , wherein the semiconductor channel is a layer of a stack of semiconductor channel layers, each between two vertically adjacent sacrificial layers, the method further comprising:
removing a first portion of the sacrificial layers exposed in the source/drain trenches to form first gaps between two vertically adjacent semiconductor channel layers; and
forming spacer layers in the first gaps wherein the epitaxially growing of the second epitaxial layers includes epitaxially growing the second epitaxial layers on sidewall surfaces of the spacer layers.
19. The method of claim 17 , wherein the source/drain trenches are first source/drain trenches in a first region of the substrate, the semiconductor channel is a first semiconductor channel in the first region, and the semiconductor structure includes second source/drain trenches in a second region of the substrate and a second semiconductor channel in the second region, the method further comprising:
epitaxially growing fourth epitaxial layers on bottom surfaces and sidewall surfaces of the second source/drain trenches, wherein the fourth epitaxial layers are connected to the second semiconductor channel; and
epitaxially growing fifth epitaxial layers on top surfaces of the fourth epitaxial layers, wherein the fourth and fifth epitaxial layers are doped with a dopant that has a conductivity type opposite to that of the first, second, and third dopants.
20. The method of claim 17 , wherein the epitaxially growing of the second epitaxial layers includes epitaxially growing the second epitaxial layers spaced away from the substrate.