Semiconductor device
A semiconductor device is provided. A semiconductor device comprising a first active pattern including a first lower pattern and a plurality of first sheet patterns spaced apart from the first lower pattern in a first direction and having a first source/drain recess formed therein, a first source/drain pattern filling the first source/drain recess and in contact with the first sheet patterns on the first lower pattern, and first gate structures disposed on both sides of the first source/drain pattern in a second direction different from the first direction and each including first gate electrodes each surrounding the plurality of first sheet patterns, wherein the first source/drain pattern includes a first region on the first lower pattern, second regions including impurities of a conductivity type different from that of the first region and in contact with the first region and side surfaces of the first sheet patterns, and a third region between the second regions, and a thickness of the first region in the first direction is greater than a thickness of the second region.
1 . A semiconductor device comprising:
a first active pattern including a first lower pattern and a plurality of first sheet patterns spaced apart from the first lower pattern in a first direction and having a first source/drain recess formed therein;
a first source/drain pattern filling the first source/drain recess and in contact with the plurality of first sheet patterns on the first lower pattern; and
first gate structures disposed on both sides of the first source/drain pattern in a second direction different from the first direction and each including first gate electrodes surrounding the plurality of first sheet patterns,
wherein the first source/drain pattern includes:
a first region on the first lower pattern,
second regions including impurities of a conductivity type different from a conductivity type of the first region, wherein the second regions include a first portion in contact with the first region and second portions in contact with side surfaces of the plurality of first sheet patterns, and
a third region between the second regions, and
wherein a thickness of the first region in the first direction is greater than a thickness of the first portion of the second region in the first direction.
2 . The semiconductor device of claim 1 , wherein the first source/drain recess is disposed in the first lower pattern, and
the first region is disposed in the first source/drain recess and in contact with the first lower pattern at a bottom surface of the first source/drain recess.
3 . The semiconductor device of claim 1 , wherein a height of an upper surface of the first region is lower than or the same as a height of an upper surface of the first lower pattern adjacent to the first source/drain recess.
4 . The semiconductor device of claim 1 , further comprising:
a second active pattern including a second lower pattern and a plurality of second sheet patterns;
a second source/drain pattern disposed on the second lower pattern, in contact with the second sheet patterns, and including impurities of a conductivity type different from that of the first source/drain pattern; and
second gate structures disposed on both sides of the second source/drain pattern,
wherein the second source/drain pattern is disposed in a second source/drain recess, and
a depth of the first source/drain recess is greater than a depth of the second source/drain recess.
5 . The semiconductor device of claim 1 , wherein the first gate structures include a first inner spacer between a pair of the plurality of first sheet patterns that are adjacent to each other in the first direction, and
wherein the first inner spacer is disposed between one of the first gate electrodes and the first source/drain pattern.
6 . The semiconductor device of claim 1 , wherein a side surface of one of the plurality of first sheet patterns comprises a concave portion, and
a length of the one of the plurality of first sheet patterns in the second direction is smaller than a length of each of the first gate structures in the second direction.
7 . The semiconductor device of claim 1 , wherein the first region includes impurities that cause the conductivity type of the first region to be different from a conductivity type of the second regions and a conductivity type of the third region.
8 . The semiconductor device of claim 7 , wherein a concentration of the impurities in the first region is lower than a concentration of the impurities in the second regions, and
the concentration of the impurities in the second regions is lower than a concentration of impurities in the third region.
9 . The semiconductor device of claim 1 , wherein the second regions include a first n-type impurity and the third region includes a second n-type impurity different from the first n-type impurity.
10 . A semiconductor device comprising:
a first active pattern including a first lower pattern and a plurality of first sheet patterns spaced apart from the first lower pattern in a first direction;
a plurality of first gate structures spaced apart from each other in a second direction, different from the first direction, on the first lower pattern, and each including first gate electrodes surrounding the plurality of first sheet patterns;
a first source/drain recess defined between a pair of the plurality of first gate structures that are adjacent to each other in the first direction; and
a first source/drain pattern disposed in the first source/drain recess on the first lower pattern,
wherein the first gate structure further includes a first inner spacer between a pair of the plurality of first sheet patterns that are adjacent to each other in the first direction,
wherein the first source/drain pattern includes:
a first semiconductor region on the first lower pattern, wherein the first semiconductor region contacts the first lower pattern at a bottom surface of the first source/drain recess,
a plurality of second semiconductor regions composed of a same material, wherein the plurality of second semiconductor regions include a first portion on and in contact with the first semiconductor region and a plurality of second portions spaced apart from each other in the first direction and in contact with side surfaces of the plurality of first sheet patterns, and wherein the plurality of second semiconductor regions include impurities of a conductivity type different from a conductivity type of the first semiconductor region, and
a third semiconductor region between the plurality of second semiconductor regions, and
wherein the first to third semiconductor regions are sequentially disposed along the first direction, and the second and third semiconductor regions are sequentially disposed along the second direction.
11 . The semiconductor device of claim 10 , wherein the first semiconductor region is disposed in the first source/drain recess of the first lower pattern, and
a height of an upper surface of the first semiconductor region is lower than or the same as a height of an upper surface of the first lower pattern adjacent to the first source/drain recess.
12 . The semiconductor device of claim 10 , further comprising:
a second active pattern including a second lower pattern and a plurality of second sheet patterns;
a second source/drain pattern disposed on the second lower pattern, in contact with the second sheet patterns, and including impurities of a conductivity type different from that of the first source/drain pattern; and
second gate structures disposed on both sides of the second source/drain pattern,
wherein the second source/drain pattern is disposed in a second source/drain recess, and
a depth of the first source/drain recess is greater than a depth of the second source/drain recess.