Transistor having wrap-around source/drain contacts

1. A method of forming a set of semiconductor devices, the method comprising:

performing fabrication operations to form a set of field effect transistor (FET) devices on a substrate, wherein the fabrication operations include:

forming a first channel region over a first region of the substrate;

forming a second channel region over a second region of the substrate and adjacent to the first channel region; and

forming over a third region of the substrate a bottom conductive layer operable to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact;

wherein the first region of the substrate, the second region of the substrate, and the third region of the substrate do not overlap;

wherein the bottom conductive layer includes a non-uniform height having a first section and a second section; and

wherein the first section tapers downward toward the first channel region and the second section tapers downward toward the second channel region.

2. The method of claim 1 further comprising:

using the first channel region and the second channel region to form a shared S/D region over the bottom conductive layer and between the first channel region and the second channel region;

wherein the shared S/D region is not a component of the multi-component S/D contact;

wherein the shared S/D region is communicatively coupled to the first channel region, the second channel region, and the bottom conductive layer;

wherein the shared S/D region is formed subsequently to forming the bottom conductive layer; and

wherein the first section tapers downward toward the first channel region and the second section tapers downward toward the second channel region such that:

portions of the bottom conductive layer that are closest to the first channel region do not contact a first sidewall of the first channel region; and

portions of the bottom conductive layer that are closest to the second channel region do not contact a first sidewall of the second channel region.

3. The method of claim 2 further comprising:

forming over the shared S/D region a top S/D contact region operable to form an upper component of the multi-component wrap-around S/D contact; and

communicatively coupling the top S/D contact region to the bottom conductive layer such that the top S/D contact region coupled to the bottom conductive layer defines a central opening;

wherein the central opening is occupied by the shared S/D region.

4. The method of claim 3 further comprising:

forming the bottom conductive layer from a first conductive material using a first set of fabrication operations; and

forming the top S/D contact region from a second conductive material using a second set of fabrication operations;

wherein the first conductive material is different than the second conductive material; and

wherein the first set of fabrication operations is different than the second set of fabrication operations.

5. The method of claim 3 , wherein a surface area of an interface between the wrap-around S/D contact and the shared S/D region comprises:

a first surface area of an interface between the shared S/D region and a first portion of a top surface of the bottom conductive layer; and

a second surface area of an interface between the top S/D contact region and the shared S/D region.

6. The method of claim 3 , wherein the shared S/D region is communicatively coupled to the bottom conductive layer through a first region of the top surface of the bottom conductive layer.

7. The method of claim 6 , wherein the top S/D contact region is communicatively coupled to the bottom conductive layer through a second region of the top surface of the bottom conductive layer.

8. The method of claim 3 , wherein:

the top S/D contact region comprises:

a contact liner;

a barrier liner; and

a conductive metal.

9. The method of claim 1 , wherein:

the first section that tapers downward toward the first channel region reduces a first capacitance between a first gate of the first channel and a shared S/D region over the bottom conductance layer; and

the second section that tapers downward toward the second channel region reduces a second capacitance between a second gate of the second channel and the shared S/D region over the bottom conductance layer.

10. A method of forming a set of semiconductor devices, the method comprising:

forming a channel region over a first region and a second region of a substrate;

forming over a third region of the substrate a bottom conductive layer operable to form a bottommost component of a multi-component wrap-around source or drain (S/D) contact;

wherein the first region of the substrate, the second region of the substrate, and the third region of the substrate do not overlap; and

forming a shared S/D region over the bottom conductive layer and adjacent to the channel region;

wherein the channel region comprises a first channel stack over the first region of the substrate and a second channel stack over the second region of the substrate;

wherein the first channel stack comprises a first set of stacked and spaced-apart channel nanosheets;

wherein the second channel stack comprises a second set of stacked and spaced-apart channel nanosheets;

wherein the shared S/D region is shared by the first channel stack and the second channel stack;

wherein a non-uniform height of the bottom conductive layer tapers downward for portions of the bottom conductive layer that are closest to the first channel stack;

wherein the non-uniform height of the bottom conductive layer tapers downward for portions of the bottom conductive layer that are closest to the second channel stack; and

wherein the shared S/D region is not a component of the multi-component S/D contact.

11. The method of claim 10 further comprising:

forming over the shared S/D region a top S/D contact region operable to form an upper component of the multi-component wrap-around S/D contact; and

communicatively coupling the top S/D contact region to the bottom conductive layer such that the top S/D contact region coupled to the bottom conductive layer defines a central opening;

wherein the central opening is occupied by the shared S/D region.

12. The method of claim 11 , wherein forming the shared S/D region comprises:

epitaxially growing the shared S/D region from the first set of stacked and spaced-apart channel nanosheets; and

epitaxially growing the shared S/D region from the second set of stacked and spaced-apart channel nanosheets such that the shared S/D region extends over and is communicatively coupled to the bottom conductive layer of the wrap-around S/D contact.