Lightly-doped channel extensions

1. A semiconductor structure, comprising:

a first channel member disposed over a semiconductor substrate and a second channel member disposed over the first channel member;

a first channel extension feature coupled to the first channel member;

a second channel extension feature coupled to the second channel member;

an inner spacer feature disposed between the first channel extension feature and the second channel extension feature;

a bottom epitaxial feature disposed on a top surface of the semiconductor substrate; and

a source/drain feature disposed on and in direct contact with the bottom epitaxial feature, the first channel extension feature, the inner spacer feature and the second channel extension feature,

wherein the source/drain feature is spaced apart from the semiconductor substrate by the bottom epitaxial feature,

wherein the first channel extension feature, the second channel extension feature, and the bottom epitaxial feature are of the same composition.

2. The semiconductor structure of claim 1 ,

wherein the first channel member and the second channel member comprise silicon germanium,

wherein the first channel extension feature and the second channel extension feature comprise silicon and a p-type dopant,

wherein the first channel extension feature and the second channel extension feature are substantially free of germanium.

3. The semiconductor structure of claim 1 ,

wherein the first channel member and the second channel member comprise silicon,

wherein the first channel extension feature and the second channel extension feature comprise silicon and an n-type dopant.

4. The semiconductor structure of claim 1 , wherein a portion of the source/drain feature extends into the semiconductor substrate.

5. The semiconductor structure of claim 1 ,

wherein the first channel member and the second channel member extend lengthwise along a direction,

wherein the first channel extension feature is sandwiched between the first channel member and the source/drain feature along the direction,

wherein the second channel extension feature is sandwiched between the second channel member and the source/drain feature along the direction.

6. The semiconductor structure of claim 1 , further comprising:

a gate structure wrapping around the first channel member and the second channel member; and

a top spacer extending along a sidewall of the gate structure,

wherein the second channel extension feature is sandwiched between the inner spacer feature and the top spacer.

7. The semiconductor structure of claim 6 , wherein the gate structure is spaced apart from the first channel extension feature and the second channel extension feature.

8. The semiconductor structure of claim 6 , wherein a portion of the second channel member is sandwiched between the inner spacer feature and the top spacer.

9. The semiconductor structure of claim 1 ,

wherein the first channel member and the second channel member comprise silicon germanium and a p-type dopant,

wherein the bottom epitaxial layer comprises silicon and the p-type dopant,

wherein the bottom epitaxial layer is substantially free of germanium.

10. A semiconductor device, comprising:

a semiconductor substrate;

a first source/drain feature and a second source/drain feature, the first and second source/drain features being disposed over and in direct contact with the semiconductor substrate;

a channel member extending lengthwise between the first source/drain feature and the second source/drain feature;

a first channel extension feature sandwiched between the channel member and the first source/drain feature;

a second channel extension feature sandwiched between the channel member and the second source/drain feature;

a top spacer disposed over the first channel extension feature; and

an inner spacer feature disposed directly below and in contact with the first channel extension feature,

wherein the first source/drain feature comprises a bottom epitaxial layer in contact with the semiconductor substrate, a first epitaxial layer over the bottom epitaxial layer, and a second epitaxial layer over the first epitaxial layer,

wherein the bottom epitaxial layer comprises a first p-type dopant concentration,

wherein the first epitaxial layer comprises a second p-type dopant concentration,

wherein the second epitaxial layer comprises a third p-type dopant concentration,

wherein the first p-type dopant concentration is greater than the second p-type dopant concentration and the third p-type dopant concentration is greater than the first p-type dopant concentration.

11. The semiconductor device of claim 10 ,

wherein the channel member comprises silicon germanium,

wherein the first channel extension feature and the second channel extension feature comprise silicon and a p-type dopant.

12. The semiconductor device of claim 10 , wherein a portion of the channel member extends between the top spacer and the inner spacer feature.

13. The semiconductor device of claim 10 ,

wherein a composition of the bottom epitaxial layer is identical to a composition of the first channel extension feature and the second channel extension feature.

14. The semiconductor device of claim 10 ,

wherein the bottom epitaxial layer comprises a first germanium content,

wherein the first epitaxial layer comprises a second germanium content,

wherein the second epitaxial layer comprises a third germanium content, and

wherein the third germanium content is greater than the second germanium content and the second germanium content is greater than the first germanium content.

15. The semiconductor device of claim 14 , wherein the first germanium content is substantially zero.

16. A method, comprising:

forming a stack over a substrate, wherein the stack comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layers;

forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure comprising a channel region and a source/drain region;

forming a dummy gate stack over the channel region of the fin-shaped structure;

depositing a top spacer over the dummy gate stack;

recessing the source/drain region to form a source/drain trench that exposes portions of the substrate, sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers;

selectively and partially recessing the plurality of silicon germanium layers to form a plurality of inner spacer recesses;

forming a plurality of inner spacer features in the plurality of inner spacer recesses;

selectively trimming the plurality of silicon layers to form end surfaces;

selectively depositing a semiconductor layer on the end surfaces and the exposed portions of the substrate;

forming a source/drain feature in the source/drain trench to be in contact with the semiconductor layer and the plurality of inner spacer features;

after the forming of the source/drain feature, removing the dummy gate stack;

releasing the plurality of silicon layers in the channel region as a plurality of channel members; and

forming a gate structure around each of the plurality of channel members.

17. The method of claim 16 , wherein the semiconductor layer comprises silicon and a p-type dopant.

18. The method of claim 17 , wherein the selectively depositing of the semiconductor layer deposits the semiconductor layer on the end surfaces and a bottom surface of the source/drain trench, not on the plurality of inner spacer features.

19. The method of claim 16 , wherein, after the selectively depositing of the semiconductor layer, a portion of the semiconductor layer is disposed between the top spacer and one of the plurality of inner spacer features.

20. The method of claim 16 , wherein, after the selectively depositing of the semiconductor layer, a portion of the semiconductor layer is disposed between two of the plurality of inner spacer features.