Method of manufacturing a semiconductor device and a semiconductor device
In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
1. A semiconductor device including fin field effect transistors (FinFETs), comprising:
a first FinFET including a first source/drain epitaxial layer and a first source/drain contact disposed over the first source/drain epitaxial layer;
a second FinFET disposed adjacent to the first FinFET and including a second source/drain epitaxial layer and a second source/drain contact disposed over the second source/drain epitaxial layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact, wherein:
the dielectric layer includes a first dielectric layer in contact with the first and second source/drain contacts and a second dielectric layer disposed on the first dielectric layer, and
the dielectric layer has a tapered shape having a top width greater than a bottom width.
2. The semiconductor device of claim 1 , wherein a Ge containing layer is disposed between the dielectric layer and the first and second source/drain contacts.
3. The semiconductor device of claim 2 , wherein the first dielectric layer comprises the Ge containing layer.
4. The semiconductor device of claim 1 , wherein the first source/drain contact has a reverse tapered shape having a top width smaller than a bottom width.
5. The semiconductor device of claim 1 , further comprising an isolation insulating layer,
wherein an insulating cover layer is disposed between the isolation insulating layer and each of the first and second source/drain epitaxial layers and is in contact with the isolation insulating layer.
6. The semiconductor device of claim 1 , further comprising:
an isolation insulating layer; and
an amorphous or polycrystalline semiconductor layer made of Si, SiGe, SiC or Ge and disposed between the isolation insulating layer and each of the first and second source/drain contacts, the amorphous or polycrystalline semiconductor layer being separated from each of the first and second source/drain epitaxial layers.
7. The semiconductor device of claim 6 , wherein the semiconductor layer is amorphous Si.
8. The semiconductor device of claim 1 , wherein the first FinFET is an n-type FET and the second FinFET is a p-type FET.
9. A semiconductor device, comprising:
a fin field effect transistor (FinFET) including a fin structure, a source/drain epitaxial layer and a source/drain contact in contact with the first source/drain epitaxial layer;
an isolation insulating layer from which the fin structure protrudes;
an insulating cover layer disposed on sides of the fin structure between the isolation insulating layer and the source/drain structure and being in contact with the isolation insulating layer; and
a dielectric layer covering at least sides of the source/drain contact,
wherein the dielectric layer includes a first dielectric layer in contact with the first and second source/drain contacts and a second dielectric layer disposed on the first dielectric layer and separated from the first and second source/drain contacts by the first dielectric layer.
10. The semiconductor device of claim 9 , wherein the second dielectric layer comprises a silicon nitride based material.
11. The semiconductor device of claim 10 , wherein the second dielectric layer further comprises GeO.
12. The semiconductor device of claim 9 , wherein the source/drain contact has a reverse tapered shape having a top width smaller than a bottom width.
13. The semiconductor device of claim 9 , wherein the source/drain contact is in contact with the isolation insulating layer.
14. The semiconductor device of claim 9 , further comprising:
an amorphous or polycrystalline semiconductor layer made of Si, SiGe, SiC or Ge and disposed between the isolation insulating layer and the source/drain contact, the amorphous or polycrystalline semiconductor layer being separated from the first source/drain structure.
15. The semiconductor device of claim 14 , wherein the semiconductor layer is amorphous Si.
16. A semiconductor device, comprising:
a fin field effect transistor (FinFET) including a fin structure, a source/drain epitaxial layer and a source/drain contact in contact with the first source/drain epitaxial layer;
an isolation insulating layer from which the fin structure protrudes;
an insulating cover layer disposed on sides of the fin structure between the isolation insulating layer and the source/drain epitaxial layer and being in contact with the isolation insulating layer; and
an amorphous or polycrystalline semiconductor layer made of Si, SiGe, SiC or Ge and disposed between the isolation insulating layer and the source/drain contact.
17. The semiconductor device of claim 16 , wherein the semiconductor layer is amorphous Si.
18. The semiconductor device of claim 16 , wherein the semiconductor layer is separated from the first source/drain epitaxial layer.
19. The semiconductor device of claim 16 , wherein the semiconductor layer is thicker than the insulating cover layer.
20. The semiconductor device of claim 16 , wherein the semiconductor layer is thinner than the insulating cover layer.