Methods of manufacturing high electron mobility transistors having a modified interface region
A method of forming a high electron mobility transistor (HEMT) includes: providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate; forming a first insulating layer on the barrier layer; and forming a gate contact, a source contact, and a drain contact on the barrier layer. An interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.
1. A method of forming a high electron mobility transistor (HEMT), comprising:
providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate;
forming a first insulating layer on the barrier layer; and
forming a gate contact, a source contact, and a drain contact on the barrier layer,
wherein an interface between the first insulating layer and the barrier layer comprises a modified interface region on a drain access region and/or a source access region of the semiconductor structure such that a sheet resistance of the drain access region and/or the source access region is between 300 and 400 Ω/sq.
2. The method of claim 1 , wherein a bottom surface of the gate contact is laterally offset from the modified interface region by 10 to 400 nm.
3. The method of claim 1 , wherein forming the first insulating layer on the barrier layer comprises a use of physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), and/or thermolytic deposition.
4. The method of claim 1 , further comprising wet etching an upper surface of the barrier layer in an acidic and/or basic chemical bath prior to forming the first insulating layer.
5. The method of claim 1 , further comprising, prior to forming the first insulating layer, performing an ion bombardment of the barrier layer, performing a plasma nitridation of the barrier layer, performing a plasma oxidation of the barrier layer, performing an H2 plasma treatment of the barrier layer, and/or annealing the barrier layer in a gas environment.
6. The method of claim 1 , further comprising forming a spacer between the modified interface region and the gate contact.
7. The method of claim 6 , wherein forming the spacer comprises:
etching a hole in the first insulating layer; and
forming the spacer on a sidewall of the hole and on the barrier layer,
wherein forming the gate contact comprises forming at least a portion of the gate contact on a sidewall of the spacer in the hole.
8. The method of claim 6 , wherein an interface between the spacer and the barrier layer comprises an interface characteristic that is different from the modified interface region.
9. A method of forming a high electron mobility transistor (HEMT), comprising:
providing a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate;
forming a first insulating layer on the barrier layer;
forming a gate contact on the barrier layer, at least a portion of the gate contact within the first insulating layer; and
providing a modified interface region between the first insulating layer and the barrier layer that is laterally separated from a bottom surface of the gate contact.
10. The method of claim 9 , wherein the modified interface region is laterally separated from the bottom surface of the gate contact by 10 to 400 nm.
11. The method of claim 9 , further comprising:
etching a hole in the first insulating layer; and
forming a spacer on a sidewall of the hole and on the barrier layer,
wherein forming the gate contact comprises forming at least a portion of the gate contact on a sidewall of the spacer in the hole.
12. The method of claim 11 , wherein an interface between the spacer and the barrier layer comprises a trap concentration that is different from a trap concentration of the modified interface region.
13. The method of claim 9 , wherein providing the modified interface region comprises, prior to forming the first insulating layer, wet etching an upper surface of the barrier layer in an acidic and/or basic chemical bath, performing an ion bombardment of the barrier layer, performing a plasma nitridation of the barrier layer, performing a plasma oxidation of the barrier layer, performing an H2 plasma treatment of the barrier layer, and/or annealing the barrier layer in a gas environment.
14. The method of claim 9 , wherein a thickness of the first insulating layer is between 80 nm and 120 nm.
15. The method of claim 9 , wherein a sheet resistance of a drain access region and/or a source access region of the semiconductor structure beneath the modified interface region is between 300 and 400 Ω/sq.
16. A method of forming a high electron mobility transistor (HEMT), comprising:
providing a semiconductor structure comprising a channel layer on a substrate and a barrier layer on the channel layer;
forming a first insulating layer on the barrier layer and etching an opening in the first insulating layer, the first insulating layer comprising a modified interface region in an interface between the first insulating layer and the barrier layer;
forming a spacer on the barrier layer in the opening in the first insulating layer; and
forming a gate contact on the barrier layer and the spacer in the opening in the first insulating layer,
wherein an interface between the spacer and the barrier layer comprises a trap concentration and/or surface potential that is different from a trap concentration and/or surface potential of the modified interface region.
17. The method of claim 16 , further comprising thinning the substrate.
18. The method of claim 16 , wherein a bottom corner of the gate contact is offset from the modified interface region by the spacer.
19. The method of claim 16 , wherein a thickness of the first insulating layer is between 80 nm and 120 nm.
20. The method of claim 16 , wherein a width of a bottom surface of the spacer that is adjacent the barrier layer is 10 to 400 nm.
21. The method of claim 16 , wherein forming the first insulating layer comprising the modified interface region comprises:
wet etching an upper surface of the barrier layer in an acidic and/or basic chemical bath, performing a buffered oxide etch (BOE) of the upper surface of the barrier layer, performing an ion bombardment of the barrier layer, performing a plasma nitridation of the barrier layer, performing a plasma oxidation of the barrier layer, performing an H2 plasma treatment of the barrier layer, and/or annealing the barrier layer in a gas environment; and
depositing a passivation layer on the barrier layer.