IP Library › Granted Patent US 12,002,865
Granted Patent B2
US 12,002,865 · App. 17/326,848 · Granted Jun 4, 2024

Interconnect features with sharp corners and method forming same

Inventor: Tze-Liang Lee (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/42376H01L21/823418H01L21/823431H01L21/823456H01L21/823475H01L27/0886H01L29/401H01L29/41791H01L29/4236H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 12,002,865
App. No.
17/326,848
Granted
Jun 4, 2024
Kind
B2
Abstract

A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.

Claims (53)

1. A method comprising:

depositing a dielectric layer;

depositing a plurality of mandrel strips over the dielectric layer;

forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups, wherein each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups;

forming a mask strip connecting two neighboring mask groups in the plurality of mask groups;

reducing a top surface of the mask strip to be level with or lower than top surfaces of the plurality of mask groups, wherein the reducing the top surface of the mask strip comprises:

polishing the mask strip; and

after the polishing, etching down the mask strip;

using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer, and to form trenches in the dielectric layer; and

filling a conductive material into the trenches to form a plurality of conductive features.

2. The method of claim 1 , wherein the forming the plurality of spacers comprises depositing a blanket layer, and performing an anisotropic etching process on the blanket layer.

3. The method of claim 1 , wherein the forming the mask strip comprises:

depositing a template layer over the plurality of mask groups, wherein the template layer has a top surface higher than the top surfaces of the plurality of mask groups;

forming an opening in the template layer, wherein at least two of the plurality of mask groups are revealed through the opening;

filling the opening to form the mask strip; and

removing the template layer.

4. The method of claim 1 , wherein the plurality of conductive features have lengthwise directions aligned to a straight line, and the plurality of conductive features comprises an end strip comprising a first end and a second end, wherein the first end is curved and has a first radius, and the second end is curved and has a second radius smaller than the first radius.

5. The method of claim 4 , wherein a ratio of the first radius to the second radius is greater than about 2.0.

6. The method of claim 1 , wherein the depositing the dielectric layer comprises depositing a low-k dielectric layer.

7. The method of claim 1 , wherein the top surface of the mask strip is reduced to be level with the top surfaces of the plurality of mask groups.

8. The method of claim 1 , wherein the top surface of the mask strip is reduced to be lower than the top surfaces of the plurality of mask groups.

9. The method of claim 5 , wherein the ratio of the first radius to the second radius is greater than about 3.0.

10. The method of claim 4 , wherein the first end is continuously curved, and the second end comprises two curved corner portions and a substantially straight portion connected the two curved corner portions.

11. A method comprising:

forming a dielectric layer;

etching the dielectric layer to form openings; and

forming a plurality of conductive features, with at least upper portions of the conductive features filling the openings in the dielectric layer, wherein the plurality of conductive features have lengthwise directions aligned to a same straight line, wherein the plurality of conductive features comprise a first end feature, a second end feature, and at least one middle conductive feature between, and physically separated from, the first end feature and the second end feature, and the first end feature comprising:

a first end facing away from the second end feature, wherein the first end have first corners; and

a second end facing toward the second end feature, wherein the second end have second corners sharper than the first corners.

12. The method of claim 11 , further comprising forming an etching mask comprising:

a spacer forming a ring encircling an additional opening, the spacer comprising a first material; and

a mask strip separating the opening into a first portion and a second portion, wherein the mask strip is formed of a second material different from the first material; and

etching the dielectric layer to transfer the first portion and the second portion of the opening into the dielectric layer, wherein the spacer and the mask strip are used collectively as parts of a corresponding etching mask.

13. The method of claim 12 , wherein the spacer has a first height, and the mask strip has a second height lower than the first height.

14. The method of claim 12 , wherein the spacer encircle a mandrel, and the mandrel is also a part of the corresponding etching mask.

15. A method comprising:

depositing a dielectric layer;

depositing a plurality of mandrel strips over the dielectric layer;

forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups, wherein each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups;

forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, wherein the forming the mask strip comprises:

depositing a template layer over the plurality of mask groups, wherein the template layer has a top surface higher than top surfaces of the plurality of mask groups;

forming an opening in the template layer, wherein at least two of the plurality of mask groups are revealed through the opening;

filling the opening to form the mask strip; and

removing the template layer;

using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer, and to form trenches in the dielectric layer; and

filling a conductive material into the trenches to form a plurality of conductive features.

16. The method of claim 15 , wherein the forming the plurality of spacers comprises depositing a blanket layer, and performing an anisotropic etching process on the blanket layer.

17. The method of claim 15 , further comprising, reducing a top surface of the mask strip to be level with or lower than the top surfaces of the plurality of mask groups.

18. The method of claim 17 , wherein the top surface of the mask strip is reduced to be level with top surfaces of the plurality of mask groups.

19. The method of claim 17 , wherein the reducing the top surface of the mask strip comprises:

polishing the mask strip; and

after the polishing, etching-down the mask strip.

20. The method of claim 15 , wherein the plurality of conductive features have lengthwise directions aligned to a straight line, and the plurality of conductive features comprises an end strip comprising a first end and a second end, wherein the first end is curved and has a first radius, and the second end is curved and has a second radius smaller than the first radius.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2021
From: LEE, TZE-LIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 056314/0140 →
Continuity (2)
Provisional Application 63166329 · Mar 26, 2021
Related Publication 20220310815A1 · Sep 29, 2022
Cited By (1)
US 12,438,047