Three-dimensional semiconductor memory device, operating method of the same and electronic system including the same

1. A three-dimensional semiconductor memory device comprising:

a substrate;

a stack structure including interlayer dielectric layers and gate electrodes alternately stacked on the substrate; and

vertical channel structures, which are provided in channel holes penetrating the stack structure and extend in a direction perpendicular to an upper surface of the substrate,

wherein each of the vertical channel structures includes:

a data storage pattern conformally covering an inner sidewall of the channel holes and having a single-layer structure including a ferroelectric material;

a vertical channel pattern covering a sidewall of the data storage pattern and including an oxide semiconductor material;

a conductive pad on an upper surface of the vertical channel pattern; and

a vertical semiconductor pattern surrounded by the vertical channel pattern and the conductive pad,

wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern,

wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween,

wherein the substrate is a semiconductor substrate doped with an impurity of a first conductivity type, and

wherein the vertical semiconductor pattern includes semiconductor material doped with an impurity of the first conductivity type.

2. The three-dimensional semiconductor memory device of claim 1 , wherein the conductive pad includes a semiconductor material doped with an impurity of a second conductivity type different from the first conductivity type.

3. The three-dimensional semiconductor memory device of claim 1 , wherein the data storage pattern includes at least one of HfO x having an orthorhombic crystal structure, or PZT(Pb(Zr, Ti)O 3 ), PTO(PbTiO 3 ), SBT(SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi(Sr, Ti)O 3 ), barium titanate (BaTiO 3 ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x , or InO x doped with at least one of Al, Zr, or Si.

4. The three-dimensional semiconductor memory device of claim 1 , wherein the vertical channel pattern includes an oxide semiconductor material or group-IV semiconductor material including at least one of In, Zn, or Ga.

5. The three-dimensional semiconductor memory device of claim 1 ,

wherein the data storage pattern has a pipe shape or a macaroni shape whose bottom end is opened, and

wherein the vertical channel pattern has a pipe shape or a macaroni shape whose bottom end is closed.

6. The three-dimensional semiconductor memory device of claim 1 , wherein at least a portion of the conductive pad overlaps an uppermost one among the gate electrodes in a horizontal direction.

7. The three-dimensional semiconductor memory device of claim 1 , wherein a portion of the first portion of the vertical channel pattern overlaps a lowermost one among the gate electrodes in a horizontal direction.

8. The three-dimensional semiconductor memory device of claim 1 ,

wherein the conductive pad has a step at which a width of the conductive pad changes discontinuously, and

a sidewall of the conductive pad contacts an uppermost one among the interlayer dielectric layers.

9. The three-dimensional semiconductor memory device of claim 1 , wherein each of the vertical channel structures further includes a buried insulation pattern filling a space surrounded by the vertical semiconductor pattern and the conductive pad.

10. The three-dimensional semiconductor memory device of claim 9 ,

wherein the buried insulation pattern has a step at which a width of the buried insulation pattern changes discontinuously,

a lower portion of the buried insulation pattern positioned at a lower level than the step is surrounded by the vertical semiconductor pattern,

an upper portion of the buried insulation pattern positioned at a higher level than the step is surrounded by a portion of the vertical semiconductor pattern and the conductive pad, and

a width of the upper portion is larger than a width of the lower portion.

11. The three-dimensional semiconductor memory device of claim 9 ,

wherein the conductive pad has a uniform thickness, and

a lower surface of the conductive pad is coplanar with an upper surface of the vertical semiconductor pad and an upper surface of the buried insulation pattern, and is positioned at a higher level than a lower surface of an uppermost one among the gate electrodes.

12. The three-dimensional semiconductor memory device of claim 1 ,

wherein each of the channel holes includes a first channel hole penetrating a portion of the substrate and the stack structure and a second channel hole connected to the first channel hole,

wherein the first and second channel holes have different diameters at a boundary at which the first and second channel holes are connected to each other, and

wherein each of the vertical channel structures includes a first structure filling the first channel hole and a second structure provided on the first structure and filling the second channel hole.

13. An electronic system comprising:

a three-dimensional semiconductor memory device including a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately stacked on the substrate, vertical channel structures, which are provided in channel holes penetrating the stack structure and extend in a direction perpendicular to an upper surface of the substrate, and an input/output pad electrically connected to one of the vertical channel structures; and

a controller electrically connected to the three-dimensional semiconductor memory device via the input/output pad and configured to control the three-dimensional semiconductor memory device,

wherein each of the vertical channel structures includes:

a data storage pattern conformally covering an inner sidewall of the channel holes and having a single-layer structure including a ferroelectric material;

a vertical channel pattern covering a sidewall of the data storage pattern and including an oxide semiconductor material;

a conductive pad on an upper surface of the vertical channel pattern; and

a vertical semiconductor pattern surrounded by the vertical channel pattern and the conductive pad,

wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern,

wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween, and

wherein the vertical semiconductor pattern includes semiconductor material doped with an impurity of a first conductivity type.

14. The electronic system of claim 13 ,

wherein the conductive pad includes a semiconductor material doped with an impurity of a second conductivity type different from the first conductivity type,

wherein the data storage pattern includes at least one of HfO x having an orthorhombic crystal structure, or PZT(Pb(Zr, Ti)O 3 ), PTO(PbTiO 3 ), SBT(SrBi 2 Ti 2 O 3 ), BLT(Bi(La, Ti)O 3 ), PLZT(Pb(La, Zr)TiO 3 ), BST(Bi(Sr, Ti)O 3 ), barium titanate (BaTiO 3 ), P(VDF-TrFE), PVDF, AlO x , ZnO x , TiO x , TaO x , or InO x doped with at least one of Al, Zr, or Si, and

wherein the vertical channel pattern includes an oxide semiconductor material or group-IV semiconductor material including at least one of In, Zn, or Ga.

15. The electronic system of claim 13 , wherein at least a portion of the conductive pad overlaps an uppermost one among the gate electrodes in a horizontal direction.