Semiconductor package and method of forming same

1. A method comprising:

attaching an integrated circuit die to a first insulating layer, the integrated circuit die comprising:

a substrate, a sidewall of the substrate having a first facet and a second facet, the first facet and the second facet having different slopes;

a pad over the substrate; and

a second insulating layer over the pad and the substrate, a sidewall of the second insulating layer being substantially coplanar with the first facet, wherein the second insulating layer comprises a polymer, the polymer having the following structure:

forming an encapsulant around the integrated circuit die; and

removing the second insulating layer to form a first opening in the encapsulant.

2. The method of claim 1 , wherein removing the second insulating layer comprises performing a wet etch process.

3. The method of claim 2 , wherein the wet etch process is performed using a solution comprising tetramethylammonium hydroxide (TMAH), dimethyl sulfoxide (DMSO), and water.

4. The method of claim 1 , further comprising forming a redistribution structure over the integrated circuit die and the encapsulant, wherein a third insulating layer of the redistribution structure fills the first opening.

5. The method of claim 4 , further comprising forming a second opening in the redistribution structure, wherein the second opening exposes the integrated circuit die.

6. The method of claim 1 , wherein after removing the second insulating layer a surface of the encapsulant has a roughness between 0.1 μm and 0.2 μm.

7. The method of claim 1 , further comprising:

forming through vias on the first insulating layer, wherein forming the encapsulant comprises forming the encapsulant along sidewalls of the through vias.

8. A method comprising:

forming a first die and a second die on a wafer, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, a first contact pad over the first interconnect structure, and a first sacrificial layer over the first contact pad, wherein the second die comprises a second substrate, a second interconnect structure over the second substrate, a second contact pad over the second interconnect structure, and a second sacrificial layer over the second contact pad;

singulating the first die from the second die, wherein an upper sidewall of the first die is beveled;

placing the first die on a substrate;

forming an encapsulant over the substrate, the encapsulant extending along sidewalls of the first interconnect structure and the first sacrificial layer;

fully removing the first sacrificial layer to expose the first contact pad; and

forming a conductive feature contacting the first contact pad.

9. The method of claim 8 , further comprising:

after removing the first sacrificial layer, forming an insulating layer over the first contact pad; and

forming a first opening through the insulating layer, wherein the conductive feature extends through the first opening to the first contact pad.

10. The method of claim 9 , wherein the conductive feature extends over an upper surface of the insulating layer.

11. The method of claim 9 , wherein the first die comprises sensing elements over the first interconnect structure, wherein forming the insulating layer comprises forming the insulating layer over the sensing elements, further comprising:

forming a second opening to expose the sensing elements.

12. The method of claim 9 , wherein the insulating layer comprises a carbonyl group including an ester group.

13. The method of claim 8 , wherein singulating comprises forming a groove between the first die and the second die, wherein the groove has a first width at a top of the groove, wherein the groove has a second width at a bottom of the groove, wherein the second width is less than the first width.

14. The method of claim 13 , wherein the second width is about 65% of the first width.

15. A method comprising:

forming a first redistribution structure on a carrier substrate;

forming a through via on the first redistribution structure;

attaching a first die to the first redistribution structure, the first die comprising a substrate, an interconnect structure over the substrate, and a first insulating layer over the interconnect structure, an upper sidewall of the first insulating layer being tapered with respect to a lower sidewall of the substrate;

forming an encapsulant over the first redistribution structure, wherein the first insulating layer is exposed;

removing at least a portion of the first insulating layer to expose a sidewall of the encapsulant, the sidewall of the encapsulant facing the interconnect structure;

forming a second insulating layer over the encapsulant and over the interconnect structure;

forming a first opening in the second insulating layer to expose a contact pad of the first die; and

forming an electrical contact in the opening.

16. The method of claim 15 , wherein an angle between the upper sidewall of the first insulating layer and a major surface of the interconnect structure is between 50° and 70°.

17. The method of claim 15 , wherein removing at least the portion of the first insulating layer roughens a surface of the encapsulant and a surface of the through via.

18. The method of claim 15 , wherein the second insulating layer directly contacts a sidewall of the encapsulant.

19. The method of claim 15 , wherein the first die comprises sensors along a top surface of the interconnect structure, further comprising:

forming a second opening in the second insulating layer to expose the sensors.

20. The method of claim 8 , wherein the first sacrificial layer comprises a polyimide with an ester group.