Diagonal via pattern and method

1. A method of generating an integrated circuit (IC) layout diagram, the method comprising:

obtaining a grid comprising grid intersections of first and second pluralities of tracks corresponding to adjacent metal layers;

determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule;

applying a via positioning pattern to the grid whereby via region placement is restricted to alternating diagonal grid lines;

positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines; and

generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

2. The method of claim 1 , wherein the determining that the first and second pitches of the respective first and second pluralities of tracks conform to the first rule comprises determining that at least one of the first or second pitches is less than a minimum via spacing rule.

3. The method of claim 1 , wherein the determining that the first and second pitches of the respective first and second pluralities of tracks conform to the first rule comprises determining that a ratio of a greater one of the first or second pitches to a lesser one of the first or second pitches is less than √{square root over ( 3 )}.

4. The method of claim 1 , wherein the first pitch is greater than the second pitch.

5. The method of claim 4 , wherein the first pitch corresponds to a first direction, and the second pitch corresponds to a cell height direction perpendicular to the first direction.

6. The method of claim 4 , wherein the first plurality of tracks corresponds to an upper metal layer of the adjacent metal layers, and the second plurality of tracks corresponds to a lower metal layer of the adjacent metal layers.

7. The method of claim 1 , wherein

the alternating diagonal grid lines are a first set of alternating grid lines, and

the applying the via positioning pattern to the grid comprises applying forbidden regions along a second set of alternating diagonal grid lines between the first set of alternating grid lines.

8. The method of claim 7 , wherein the applying the forbidden regions comprises applying forbidden positions at intersections of the first and second pluralities of tracks.

9. The method of claim 1 , further comprising applying a metal design rule to a metal layer of the adjacent metal layers.

10. The method of claim 9 , wherein the applying the metal design rule comprises reducing one or more of an enclosure rule or an end-to-end spacing rule of the metal layer of the adjacent metal layers.

11. The method of claim 9 , wherein the applying the metal design rule comprises dividing the first or second plurality of tracks of the metal layer into two track subsets having different pitches.

12. The method of claim 11 , wherein the different pitches have a pitch difference less than a manufacturing tolerance value.

13. A method of generating an integrated circuit (IC) layout diagram, the method comprising:

obtaining a grid comprising grid intersections of first and second pluralities of tracks corresponding to adjacent metal layers, wherein the first and second pluralities of tracks have respective first and second pitches;

confirming that one or both of:

the first and/or second pitch is less than a minimum via spacing rule, or

a ratio of a greater one of the first or second pitches to a lesser one of the first or second pitches is less than √{square root over ( 3 )};

applying a via positioning pattern to the grid whereby via region placement is restricted to alternating diagonal grid lines;

positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines; and

generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

14. The method of claim 13 , wherein

the first pitch corresponds to a cell height direction, and

the second pitch is greater than the first pitch.

15. The method of claim 14 , wherein the first plurality of tracks corresponds to one of the adjacent metal layers overlying the other of the adjacent metal layers corresponding to the second plurality of tracks.

16. The method of claim 15 , further comprising applying a metal design rule to the other of the adjacent metal layers.

17. The method of claim 16 , wherein the positioning the vias regions comprises overlapping one or more metal regions of the other of the adjacent metal layers positioned based on the metal design rule.

18. A method of generating an integrated circuit (IC) layout diagram, the method comprising:

obtaining a grid comprising grid intersections of first and second pluralities of tracks corresponding to adjacent metal layers;

determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule;

applying a via positioning pattern to the grid by applying a second rule forbidding placing via regions at potential via locations at intersections of the first and second pluralities of tracks, wherein the potential via locations correspond to a first set of diagonal grid lines;

positioning via regions at some or all of the grid intersections of a second set of diagonal grid lines alternating with the first set of alternating diagonal grid lines; and

generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

19. The method of claim 18 , wherein the determining that the first and second pitches of the respective first and second pluralities of tracks conform to the first rule comprises one or both of:

determining that at least one of the first or second pitches is less than a minimum via spacing rule, or

determining that a ratio of a greater one of the first or second pitches to a lesser one of the first or second pitches is less than √{square root over ( 3 )}.

20. The method of claim 18 , wherein the applying the second rule forbidding placing via regions at potential via locations comprises applying forbidden regions at the intersections of the first and second pluralities of tracks.