Semiconductor package and method of manufacturing the semiconductor package
A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.
1. A semiconductor package, comprising:
a support member;
a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface, respectively;
a lower redistribution wiring layer covering the second surface of the support member and the front surface of the semiconductor chip, and including a plurality of first redistribution wirings electrically connected to a plurality of chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member, respectively; and
an upper redistribution wiring layer covering the first surface of the support member and the backside surface of the semiconductor chip, and including a plurality of second redistribution wirings electrically connected to the vertical connection structures and a metallic thermal pattern provided on the exposed backside surface of the semiconductor chip.
2. The semiconductor package of claim 1 , further comprising:
a sealing layer covering the first surface of the support member and exposing the backside surface of the semiconductor chip.
3. The semiconductor package of claim 2 ,
wherein the backside surface of the semiconductor chip is higher than the first surface of the support member, and
wherein the backside surface of the semiconductor chip is coplanar with an upper surface of the sealing layer.
4. The semiconductor package of claim 3 ,
wherein the upper redistribution wiring layer further includes a protective layer pattern on an upper surface of the sealing layer.
5. The semiconductor package of claim 1 ,
wherein the upper redistribution wiring layer further includes a barrier layer provided between the thermal pattern and the backside surface of the semiconductor chip.
6. The semiconductor package of claim 5 ,
wherein the barrier layer includes at least one of a seed layer, an oxide layer, and an adhesive layer.
7. The semiconductor package of claim 1 ,
wherein the thermal pattern includes a first thickness, and
wherein each of the plurality of first redistribution wirings has a second thickness less than the first thickness.
8. The semiconductor package of claim 7 ,
wherein the first thickness of the thermal pattern has a value from 3 μm to 50 μm, and
wherein the second thickness of each of the plurality of first redistribution wirings has a value from 3 μm to 8 μm.
9. The semiconductor package of claim 1 ,
wherein the plurality of second redistribution wirings includes a first upper redistribution wiring and a second upper redistribution wiring stacked in at least two levels.
10. The semiconductor package of claim 9 ,
wherein the upper redistribution wiring layer further includes a ground pattern coplanar with the second upper redistribution wiring and electrically connected to the thermal pattern.
11. A semiconductor package, comprising:
a substrate having a cavity;
at least one semiconductor chip arranged within the cavity, and having a plurality of chip pads provided at a front surface of the semiconductor chip;
a sealing layer covering a first surface of the substrate, and filling the cavity such that a backside surface of the semiconductor chip is exposed from the sealing layer;
a lower redistribution wiring layer covering a second surface of the substrate opposite to the first surface, and including a plurality of first redistribution wirings electrically connected to the plurality of chip pads;
an upper redistribution wiring layer covering the first surface of the substrate, and including a plurality of second redistribution wirings electrically connected to a plurality of connection wirings and a thermal pattern provided on the exposed backside surface of the semiconductor chip; and
a plurality of outer connection members arranged on an outer surface of the lower redistribution wiring layer and electrically connected to the plurality of first redistribution wirings,
wherein the backside surface of the semiconductor chip is coplanar with an upper surface of the sealing layer, and
a first thickness of the thermal pattern has a value from 3 μm to 50 μm.
12. The semiconductor package of claim 11 ,
wherein the upper redistribution wiring layer further includes a barrier layer provided between the thermal pattern and the backside surface of the semiconductor chip.
13. The semiconductor package of claim 12 ,
wherein the barrier layer includes at least one of a seed layer, an oxide layer, and an adhesive layer.
14. The semiconductor package of claim 11 ,
wherein the plurality of second redistribution wirings include a first upper redistribution wiring and a second upper redistribution wiring stacked in two levels, and
wherein the thermal pattern is coplanar with the first upper redistribution wiring.
15. The semiconductor package of claim 14 ,
wherein the upper redistribution wiring layer further includes a ground pattern electrically connected to the thermal pattern.
16. A semiconductor package, comprising:
a lower redistribution wiring layer including a plurality of first redistribution wirings stacked in two levels;
a semiconductor chip arranged on the lower redistribution wiring layer, and having a plurality of chip pads provided at a front surface to be electrically connected to the plurality of first redistribution wirings;
a support member on the lower redistribution wiring layer to surround the semiconductor chip, and exposing a backside surface of the semiconductor chip; and
an upper redistribution wiring layer on the support member, and including a plurality of second redistribution wirings electrically connected to a plurality of vertical connection structures that penetrate at least a portion of the support member, and a metallic thermal pattern provided on the exposed backside surface of the semiconductor chip.
17. The semiconductor package of claim 16 ,
wherein the upper redistribution wiring layer further includes a barrier layer provided between the thermal pattern and the backside surface of the semiconductor chip.
18. The semiconductor package of claim 17 ,
wherein the barrier layer includes at least one of a seed layer, an oxide layer, and an adhesive layer.
19. The semiconductor package of claim 16 ,
wherein a thickness of the thermal pattern has a value from 3 μm to 50 μm.
20. The semiconductor package of claim 16 ,
wherein the plurality of second redistribution wirings include a first upper redistribution wiring and a second upper redistribution wiring stacked in at least two levels, and
wherein the thermal pattern is coplanar with the first upper redistribution wiring.