IP Library Granted Patent US 11,700,696
Granted Patent B2
US 11,700,696 · App. 17/338,450 · Granted Jul 11, 2023

Buried electrical debug access port

Inventors: Florence R. Neumann (Folson, CA); Bilal Khalaf (Folsom, CA); Saeed S. Shojaie (Folsom, CA)
Assignee: Intel Corporation
H05K3/284G01R31/2818H01L2224/16225H01L2924/15311H01L2924/181
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Quick Facts
Patent No.
US 11,700,696
App. No.
17/338,450
Granted
Jul 11, 2023
Kind
B2
Abstract

Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.

Claims (20)

1. A method for fabricating an apparatus, the method comprising:

coupling one or more electronic components with a substrate or a printed circuit board;

coupling an electrical access port with the substrate or printed circuit board, the electrical access port including electrically conductive material; and

encapsulating the electrical access port with an encapsulant material, the encapsulant material having a top surface, a bottom surface, and side surfaces between the top surface and the bottom surface, wherein the bottom surface is on the substrate or printed circuit board, and wherein the encapsulant material has an opening in one of the side surfaces, the opening extending through the encapsulant material and exposing at least one of the electrical access port, wherein the electrical access port has a surface proximate the one of the side surfaces of the encapsulant material, and the opening exposes a portion of but not all of the surface of the electrical access port, wherein the electrical access port is electrically connected to one or more circuits of the apparatus.

2. The method of claim 1 , wherein each of the electrical access port is insulated from electrical contact by the encapsulant material.

3. The method of claim 1 , wherein the apparatus is a system in package (SiP).

4. The method of claim 1 , wherein the electrical access port is adjacent to an edge of the encapsulant material.

5. The method of claim 1 , wherein the electrical access port is a closest element of the apparatus to an edge of the encapsulant material.

6. The method of claim 1 , wherein the electrical access port is a closest element of the apparatus to a top surface of the encapsulant material.

7. The method of claim 1 , wherein the electrical access port is accessible by breaking through the encapsulate material.

8. The method of claim 1 , wherein breaking through the encapsulate material includes drilling through or piercing through the encapsulate material.

9. The method of claim 1 , wherein the electrical access port is accessible by electromagnetic coupling with at least one access port.

10. A method of fabricating a system, the method comprising:

coupling a processor to a motherboard;

coupling an electronic package to the motherboard, wherein the electronic package includes:

a substrate or printed circuit board, a plurality of electronic components including a solid state drive (SSD) coupled with the substrate or printed circuit board, an electrical access port coupled with the substrate or printed circuit board, the electrical access port including electrically conductive material, and an encapsulant material, wherein the encapsulant material encapsulates the electrical access port, the encapsulant material having a top surface, a bottom surface, and side surfaces between the top surface and the bottom surface, wherein the bottom surface is on the substrate or printed circuit board, and wherein the encapsulant material has an opening in one of the side surfaces, the opening extending through the encapsulant material and exposing at least one of the electrical access port, wherein the electrical access port has a surface proximate the one of the side surfaces of the encapsulant material, and the opening exposes a portion of but not all of the surface of the electrical access port;

wherein the electrical access port is electrically connected to one or more circuits of the electronic package to provide debugging access to the electronic package.

11. The method of claim 10 , wherein each of the electrical access port is insulated from electrical contact by the encapsulant material.

12. The method of claim 10 , wherein the electrical access port is adjacent to an edge of the encapsulant material.

13. The method of claim 10 , wherein the electrical access port is a closest element of the apparatus to an edge of the encapsulant material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072915/0744 →
Continuity (2)
Division 15089385 · Apr 1, 2016
Related Publication 20210298183A1 · Sep 23, 2021