Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
1. A method for controlling a memory device,
the memory device, including:
a memory cell array including a memory block, the memory block including a first sub memory block and a second sub memory block, the first sub memory block including a plurality of first memory cells, and the second sub memory block including a plurality of second memory cells;
a first drain side selective transistor connected to the first memory cells;
a second drain side selective transistor connected to the second memory cells;
a first source side selective transistor connected to the first memory cells;
a second source side selective transistor connected to the second memory cells;
a first source line connected to the first source side selective transistor and the second source side selective transistor;
a plurality of first word lines connected to gates of the first memory cells;
a plurality of second word lines connected to gates of the second memory cells;
a plurality of first control gate lines connected to the plurality of first word lines not via any of the plurality of the second word lines;
a plurality of second control gate lines connected to the plurality of second word lines not via any of the plurality of the first word lines;
a first source side select gate line connected to a gate of the first source side selective transistor; and
a second source side select gate line connected to a gate of the second source side selective transistor;
the method including:
performing an erase operation of erasing data stored in the plurality of first memory cells in the first sub memory block, while erasing data stored in the plurality of second memory cells in the second sub memory block being prohibited.
2. The method for controlling the memory device according to claim 1 , wherein
the first source side select gate line and the second source side select gate line are electrically disconnected from each other and capable to apply a voltage independently.
3. The method for controlling the memory device according to claim 1 , further comprising:
a plurality of third memory cells connected between the first drain side selective transistor and the first source side selective transistor;
a first joining portion joining the first memory cells and the third memory cells in series;
a plurality of fourth memory cells connected between the second drain side selective transistor and the second source side selective transistor; and
a second joining portion joining the second memory cells and the fourth memory cells in series.
4. The method for controlling the memory device according to claim 1 , wherein
one of the first word lines and a corresponding one of the second word lines are disposed in the same layer, respectively.
5. The method for controlling the memory device according to claim 1 , wherein
one of the first word lines and a corresponding one of the second word lines are electrically disconnected from each other.
6. The method for controlling the memory device according to claim 3 , wherein
the first joining portion and the second joining portion, include poly silicon.
7. The method for controlling the memory device according to claim 3 , wherein
the plurality of first memory cells are arranged in one straight line, the plurality of third memory cells are arranged in another straight line.
8. The method for controlling the memory device according to claim 3 , wherein
the plurality of first memory cells are arranged in one straight line, the plurality of third memory cells are arranged in another straight line parallel to the one straight line.
9. The method for controlling the memory device according to claim 3 , wherein
the plurality of first memory cells and the plurality of third memory cells are approximately arranged in one straight line.
10. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line, and
the first voltage is lower than the second voltage.
11. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line, and
a timing of applying the first voltage is later than a timing of applying the second voltage.
12. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
the first voltage is lower than the third voltage.
13. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
the first voltage is lower than the third voltage,
a timing of applying the third voltage is earlier than a timing of applying the first voltage.
14. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
the first voltage is lower than the third voltage,
a timing of applying the third voltage is earlier than a timing of applying the first voltage, and
the timing of applying the third voltage is earlier than a timing of applying the second voltage.
15. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line, and
a timing of applying the third voltage is earlier than a timing of applying the first voltage.
16. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
a timing of applying the third voltage is earlier than a timing of applying the first voltage, and
the timing of applying the third voltage is earlier than a timing of applying the second voltage.
17. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
applying a fourth voltage to one of the first word lines,
applying a fifth voltage to one of the second word lines,
the first voltage is lower than the third voltage, and
the fourth voltage is lower than the first voltage.
18. The method for controlling the memory device according to claim 1 , wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
applying a fourth voltage to one of the first word lines,
applying a fifth voltage to one of the second word lines,
the first voltage is lower than the third voltage,
the fourth voltage is lower than the second voltage, and
a difference between the first voltage and the second voltage is smaller than a difference between the second voltage and the fourth voltage.
19. The method for controlling the memory device according to claim 1 , further comprising
a plurality of first dummy word lines connected between the first drain side selective transistor and the first source side selective transistor,
a plurality of second dummy word lines connected between the second drain side selective transistor and the second source side selective transistor, wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
applying a fourth voltage to one of the first word lines,
applying a fifth voltage to one of the second word lines,
applying a sixth voltage to one of the first dummy word lines,
applying a seventh voltage to one of the second dummy word lines,
the first voltage is lower than the third voltage,
the sixth voltage is lower than the first voltage, and
the fourth voltage is lower than the sixth voltage.
20. The method for controlling the memory device according to claim 1 , further comprising
a plurality of first dummy word lines connected between the first drain side selective transistor and the first source side selective transistor,
a plurality of second dummy word lines connected between the second drain side selective transistor and the second source side selective transistor, wherein
the erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the first source line,
applying a fourth voltage to one of the first word lines,
applying a fifth voltage to one of the second word lines,
applying a sixth voltage to one of the first dummy word lines,
applying a seventh voltage to one of the second dummy word lines,
the first voltage is lower than the third voltage,
the sixth voltage is lower than the first voltage,
the fourth voltage is lower than the sixth voltage,
a timing of applying the third voltage is earlier than a timing of applying the first voltage, and
the timing of applying the third voltage is earlier than a timing of applying the second voltage.
21. The method for controlling the memory device according to claim 20 , wherein
a distance between a gate of the first drain side selective transistor and one of the nearest gates of the first memory cells is longer than a distance between the gates of the first memory cells.
22. The method for controlling the memory device according to claim 20 , wherein
a distance between a gate of the first drain side selective transistor and one of the nearest gates of the first memory cells is doubled or more than a distance between the gates of the first memory cells.
23. The method for controlling the memory device according to claim 20 , wherein
a distance between the gate of the second source side selective transistor and one of the nearest gates of the second memory cells is longer than a distance between the gates of the second memory cells.
24. The method for controlling the memory device according to claim 20 , wherein
a distance between the gate of the second source side selective transistor and one of the nearest gates of the second memory cells is doubled or more than a distance between the gates of the second memory cells.
25. The method for controlling the memory device according to claim 20 , further comprising
a plurality of third memory cells,
a first joining portion joining the first memory cells and the third memory cells in series,
a plurality of fourth memory cells,
a second joining portion joining the second memory cells and the fourth memory cells in series, wherein
the first joining portion and the second joining portion, include poly silicon.
26. The method for controlling the memory device according to claim 1 , further comprising:
a plurality of third memory cells connected between the first drain side selective transistor and the first source side selective transistor;
a plurality of fourth memory cells connected between the second drain side selective transistor and the second source side selective transistor;
a plurality of third word lines connected to gates of the third memory cells; and
a plurality of fourth word lines connected to gates of the fourth memory cells,
the plurality of first control gate lines being connected to the plurality of fourth word lines not via any of the plurality of the second word lines or any of the plurality of the third word lines, and
the plurality of second control gate lines being connected to the plurality of third word lines not via any of the plurality of the first word lines or any of the plurality of the fourth word lines.