Integrated circuit structure and method with hybrid orientation for FinFET
The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
1. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region;
a first fin of a first semiconductor material disposed within the first region, wherein the first fin has a first crystalline direction along a first direction, wherein the first fin includes a single channel; and
a second fin of a second semiconductor material disposed within the second region, wherein the second fin has a second crystalline direction along the first direction, wherein the second crystalline direction is different from the first crystalline direction, and wherein the second fin includes plurality of channels vertically stacked and vertically spaced away from each other, and wherein the second semiconductor material is different from the first semiconductor material in composition.
2. The semiconductor structure of claim 1 , wherein the first crystalline direction is a <100> crystalline direction, and the second crystalline direction is a <110> crystalline direction.
3. The semiconductor structure of claim 2 , wherein
each of the first fin and the second fin is in a crystalline structure with a top surface on a (100) crystal plane;
the semiconductor substrate is a silicon substrate having a top surface on a (100) crystal plane; and
the semiconductor substrate has a crystalline orientation <110> along the first direction.
4. The semiconductor structure of claim 2 , further comprising:
an n-type field-effect transistor (nFET) formed on the first fin within the first region; and
a p-type field-effect transistor (pFET) formed on the second fin within the second region.
5. The semiconductor structure of claim 2 , further comprising:
a dielectric feature configured to isolate the first fin from the semiconductor substrate; and
a semiconductor layer of the first semiconductor material underlying the second fin.
6. The semiconductor structure of claim 5 , wherein
the dielectric feature spans between opposite edges of the first fin; and
the semiconductor layer spans between opposite edges of the second fin.
7. The semiconductor structure of claim 5 , wherein
the first semiconductor material is silicon,
the second semiconductor material is silicon germanium, and
the dielectric feature is a silicon oxide feature.
8. The semiconductor structure of claim 5 , further comprising a shallow trench isolation (STI) feature formed in the semiconductor substrate and surrounding the first fin, wherein the STI feature has a sidewall directly contacting a sidewall of the dielectric feature.
9. The semiconductor structure of claim 8 , wherein
the STI feature has a top surface being coplanar with a top surface of the dielectric feature and a top of the semiconductor layer;
the semiconductor layer includes a bottom surface being coplanar with a bottom surface of the dielectric feature; and
the first fin continuously extends to the dielectric feature within the first region.
10. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region;
a first fin of a first semiconductor material disposed within the first region, oriented in a first direction, and being isolated from the semiconductor substrate by a dielectric feature, wherein the first fin has a <100> crystalline direction along the first direction, wherein the first fin includes a single channel;
a second fin of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin has a <110> crystalline direction along the first direction, wherein the second fin includes a plurality of channels vertically stacked and spaced away from each other;
a first fin field-effect transistor (FinFET) of a first type conductivity and formed on the first fin;
a second FinFET of a second type conductivity and formed on the second fin, wherein the second type conductivity is opposite to the first type conductivity; and
a semiconductor layer of the first semiconductor material underlying the second fin, wherein the first fin continuously extends from a top surface of the first fin to the dielectric feature.
11. The semiconductor structure of claim 10 , wherein
the first FinFET is an n-type fin field-effect transistor (nFinFET);
the first FinFET is a p-type fin field-effect transistor (pFinFET);
the first semiconductor material is silicon; and
the second semiconductor material is silicon germanium.
12. The semiconductor structure of claim 11 , wherein each of the first fin and the second fin is in a crystalline structure with a top surface on a (100) crystal plane.
13. The semiconductor structure of claim 12 , wherein
the semiconductor substrate is a silicon substrate having a top surface on a (100) crystal plane; and
the semiconductor substrate has a crystalline orientation <110> along the first direction.
14. The semiconductor structure of claim 10 , wherein
the second fin is spaced away from the first fin along a second direction that is orthogonal to the first direction;
the dielectric feature spans between opposite edges of the first fin along the second direction; and
the semiconductor layer spans between opposite edges of the second fin along the second direction.
15. The semiconductor structure of claim 10 , further comprising a shallow trench isolation (STI) feature formed in the semiconductor substrate and surrounding the first fin, wherein the STI feature has a sidewall directly contacting a sidewall of the dielectric feature.
16. The semiconductor structure of claim 15 , wherein the STI feature has a top surface being coplanar with a top surface of the dielectric feature and a top of the semiconductor layer.
17. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region;
a first fin of a first semiconductor material disposed within the first region, oriented in a first direction, and being isolated from the semiconductor substrate by a dielectric feature, wherein the first fin has a <100> crystalline direction along the first direction;
a second fin of a second semiconductor material disposed on the semiconductor substrate within the second region and oriented in the first direction, wherein the second fin has a <110> crystalline direction along the first direction, wherein the second fin is directly landing on a semiconductor feature of the first semiconductor material, and wherein the second semiconductor material being different from the first semiconductor material in composition; and
a shallow trench isolation (STI) feature formed in the semiconductor substrate, wherein the STI feature has a first sidewall contacting a sidewall of the dielectric feature and a second sidewall contacting a sidewall of the semiconductor feature.
18. The semiconductor structure of claim 17 , wherein
the second fin is spaced away from the first fin along a second direction that is orthogonal to the first direction;
the dielectric feature spans between opposite edges of the first fin along the second direction; and
the semiconductor feature spans between opposite edges of the second fin along the second direction.
19. The semiconductor structure of claim 18 , wherein each of the first fin and the second fin is in a crystalline structure with a top surface on a (100) crystal plane;
the semiconductor substrate is a silicon substrate having a top surface on a (100) crystal plane; and
the semiconductor substrate has a crystalline orientation <110> along the first direction.
20. The semiconductor structure of claim 18 , further comprising
an n-type field-effect transistor (nFET) formed on the first fin within the first region; and
a p-type field-effect transistor (pFET) formed on the second fin within the second region, wherein
the first semiconductor material is silicon;
the second semiconductor material is silicon germanium;
the dielectric feature is a silicon oxide feature;
the first fin includes a single channel continuously extends to the dielectric feature; and
the second fin includes a plurality of channels vertically stacked and spaced away from each other.