IP Library › Granted Patent US 11,849,648
Granted Patent B2
US 11,849,648 · App. 17/341,417 · Granted Dec 19, 2023

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Chen-Yi Weng (New Taipei, TW); Yi-Wei Tseng (New Taipei, TW); Chin-Yang Hsieh (Tainan, TW); Jing-Yin Jhang (Tainan, TW); Yi-Hui Lee (Taipei, TW); Ying-Cheng Liu (Tainan, TW); Yi-An Shih (Changhua County, TW); I-Ming Tseng (Kaohsiung, TW); Yu-Ping Wang (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N50/80G11C5/06G11C11/16G11C11/161H01L29/82H10N50/01H10N50/10G11C2211/5615H10B61/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,849,648
App. No.
17/341,417
Granted
Dec 19, 2023
Kind
B2
Abstract

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Claims (14)

1. A semiconductor device, comprising:

a magnetic tunneling junction (MTJ) on a substrate;

a first spacer on one side of the of the MTJ, wherein a topmost surface of the first spacer is aligned with a top surface of the MTJ;

a second spacer on another side of the MTJ;

a first metal interconnection on the MTJ; and

a liner adjacent to the first spacer, the second spacer, and the first metal interconnection, wherein a bottom surface of the liner is aligned with a bottom surface of the first spacer in a horizontal direction and the bottom surface of the liner contacts a sidewall of the first spacer.

2. The semiconductor device of claim 1 , further comprising:

a first inter-metal dielectric (IMD) layer around the liner;

a second metal interconnection under the MTJ; and

a second IMD layer around the second metal interconnection.

3. The semiconductor device of claim 1 , wherein a top surface of the MTJ comprises a planar surface.

4. The semiconductor device of claim 1 , wherein a bottom surface of the first metal interconnection comprises a planar surface.

5. The semiconductor device of claim 1 , wherein a first sidewall of the first metal interconnection is aligned with a first sidewall of the MTJ.

6. The semiconductor device of claim 1 , wherein a second sidewall of the first metal interconnection is aligned with a second sidewall of the MTJ.

Priority Claims (1)
CN 201910418706.2 · May 20, 2019 · national
Continuity (2)
Continuation 16438480 · Jun 12, 2019
Related Publication 20210296572A1 · Sep 23, 2021