IP Library Granted Patent US 11,063,206
Granted Patent B2
US 11,063,206 · App. 16/438,480 · Granted Jul 13, 2021

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Chen-Yi Weng (New Taipei, TW); Yi-Wei Tseng (New Taipei, TW); Chin-Yang Hsieh (Tainan, TW); Jing-Yin Jhang (Tainan, TW); Yi-Hui Lee (Taipei, TW); Ying-Cheng Liu (Tainan, TW); Yi-An Shih (Changhua County, TW); I-Ming Tseng (Kaohsiung, TW); Yu-Ping Wang (Taoyuan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L43/02G11C5/06G11C11/16G11C11/161H01L29/82H01L43/08H01L43/12G11C2211/5615H01L27/222
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Quick Facts
Patent No.
US 11,063,206
App. No.
16/438,480
Granted
Jul 13, 2021
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

Claims (17)

1. A semiconductor device, comprising:

a first magnetic tunneling junction (MTJ) on a substrate;

a first metal interconnection on the MTJ, wherein the first metal interconnection comprises protrusions adjacent to two sides of the MTJ and bottom surfaces of the protrusions comprise a planar surface;

a first spacer on one side of the MTJ;

a second spacer on another side of the MTJ, wherein the first spacer and the second spacer contact the protrusions directly and outer sidewalls of the protrusions are aligned with outer sidewalls of the first spacer and the second spacer; and

a liner adjacent to the first MTJ, wherein the liner contacts a sidewall of the first metal interconnection directly.

2. The semiconductor device of claim 1 , further comprising:

a first inter-metal dielectric (IMD) layer around the liner.

3. The semiconductor device of claim 1 , further comprising:

a second metal interconnection under the MTJ; and

a second IMD layer around the second metal interconnection.

4. The semiconductor device of claim 3 , wherein the MTJ comprises:

a bottom electrode on the second metal interconnection;

a barrier layer on the bottom electrode; and

a top electrode on the barrier layer.

5. The semiconductor device of claim 4 , wherein a bottom surface of the protrusions is higher than a top surface of the barrier layer.

6. The semiconductor device of claim 1 , wherein a width of the first metal interconnection is greater than a width of the MTJ.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2019
From: WANG, HUI-LIN; WENG, CHEN-YI; TSENG, YI-WEI; HSIEH, CHIN-YANG; JHANG, JING-YIN; LEE, YI-HUI; LIU, YING-CHENG; SHIH, YI-AN; TSENG, I-MING; WANG, YU-PING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 049439/0217 →
Priority Claims (1)
CN 201910418706.2 · May 20, 2019 · national
Continuity (1)
Related Publication 20200373478A1 · Nov 26, 2020
Cited By (2)
US 12,290,003 US 12,402,540