IP Library › Granted Patent US 12,402,540
Granted Patent B2
US 12,402,540 · App. 18/502,109 · Granted Aug 26, 2025

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Chen-Yi Weng (New Taipei, TW); Yi-Wei Tseng (New Taipei, TW); Chin-Yang Hsieh (Tainan, TW); Jing-Yin Jhang (Tainan, TW); Yi-Hui Lee (Taipei, TW); Ying-Cheng Liu (Tainan, TW); Yi-An Shih (Changhua County, TW); I-Ming Tseng (Kaohsiung, TW); Yu-Ping Wang (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N50/80G11C5/06G11C11/16G11C11/161H10D48/40H10N50/01H10N50/10G11C2211/5615H10B61/00
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Quick Facts
Patent No.
US 12,402,540
App. No.
18/502,109
Granted
Aug 26, 2025
Kind
B2
Abstract

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Claims (13)

1. A semiconductor device, comprising:

a magnetic tunneling junction (MTJ) on a substrate;

a first spacer on one side of the of the MTJ;

a second spacer on another side of the MTJ;

a first metal interconnection on the MTJ;

a liner adjacent to the first spacer, the second spacer, and the first metal interconnection, wherein the liner directly contacts a sidewall of the first metal interconnection;

a second metal interconnection under the MTJ, wherein a bottommost tip of a sidewall of the first spacer directly contacts a topmost tip of a sidewall of the second metal interconnection;

a first inter-metal dielectric (IMD) layer around the liner; and

a second IMD layer around the second metal interconnection, wherein the bottommost tip of the sidewall of the first spacer that directly contacts the topmost tip of the sidewall of the second metal interconnection also directly contacts a topmost tip of a sidewall of the second IMD layer.

2. The semiconductor device of claim 1 , wherein a top surface of the MTJ comprises a planar surface.

3. The semiconductor device of claim 1 , wherein a bottom surface of the first metal interconnection comprises a planar surface.

4. The semiconductor device of claim 1 , wherein a first sidewall of the first metal interconnection is aligned with a first sidewall of the MTJ.

5. The semiconductor device of claim 1 , wherein a second sidewall of the first metal interconnection is aligned with a second sidewall of the MTJ.

Priority Claims (1)
CN 201910418706.2 · May 20, 2019 · national
Continuity (3)
Continuation 17341417 · Jun 8, 2021
Continuation 16438480 · Jun 12, 2019
Related Publication 20240074328A1 · Feb 29, 2024
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