Magnetoresistive random access memory

1. A semiconductor device, comprising:

a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor on a substrate;

a magnetic tunneling junction (MTJ) between the first MOS transistor and the second MOS transistor;

a first interlayer dielectric (ILD) layer on one side of the MTJ and above and covers the first MOS transistor; and

a second ILD layer on another side of the MTJ and above and covers the second MOS transistor.

2. The semiconductor device of claim 1 , wherein the first MOS transistor comprises:

a first gate structure on the substrate;

a first spacer around the first gate structure; and

a first source/drain region on one side of the first gate structure.

3. The semiconductor device of claim 2 , wherein the second MOS transistor comprises:

a second gate structure on the substrate;

a second spacer around the second gate structure; and

a second source/drain region on one side of the second gate structure.

4. The semiconductor device of claim 3 , further comprising:

a first liner between the first spacer and the first ILD layer; and

a second liner between the second spacer and the second ILD layer.

5. The semiconductor device of claim 4 , wherein top surfaces of the first liner and the first ILD layer are coplanar.

6. The semiconductor device of claim 4 , wherein top surfaces of the second liner and the second ILD layer are coplanar.

7. The semiconductor device of claim 3 , further comprising a third source/drain region between the first gate structure and the second gate structure.

8. The semiconductor device of claim 7 , further comprising a contact plug between the first spacer and the second spacer and contacting the third source/drain region directly.

9. The semiconductor device of claim 8 , wherein the MTJ is connected to the contact plug.

10. The semiconductor device of claim 8 , wherein the MTJ is directly on top of the contact plug.

11. The semiconductor device of claim 3 , wherein the first gate structure and the second gate structure are extending along a first direction on the substrate.

12. The semiconductor device of claim 11 , further comprising a metal interconnection extending along a second direction on the first ILD layer and the second ILD layer.

13. The semiconductor device of claim 1 , wherein the first MOS transistor and the second MOS transistor comprise a same conductive type.

14. The semiconductor device of claim 1 , wherein each of the first MOS transistor and the second MOS transistor comprises a NMOS transistor.