Memory device and method for manufacturing the same
A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.
1. A memory device, comprising:
a bottom electrode;
a resistance switching element over the bottom electrode;
a top electrode over the resistance switching element;
an interlayer dielectric layer surrounding the resistance switching element;
a first spacer between the interlayer dielectric layer and a sidewall of the resistance switching element, wherein a bottom surface of the first spacer is over a top surface of the bottom electrode; and
a metal-containing compound layer between the interlayer dielectric layer and the sidewall of the resistance switching element.
2. The memory device of claim 1 , wherein the first spacer is between the resistance switching element and the metal-containing compound layer.
3. The memory device of claim 1 , wherein the metal-containing compound layer is between the resistance switching element and the first spacer.
4. The memory device of claim 1 , further comprising:
a second spacer between the interlayer dielectric layer and the first spacer.
5. The memory device of claim 4 , wherein the metal-containing compound layer is between the first spacer and the second spacer.
6. The memory device of claim 4 , wherein the second spacer is between the resistance switching element and the metal-containing compound layer.
7. The memory device of claim 4 , wherein the first spacer and the second spacer are over a portion of the metal-containing compound layer.
8. The memory device of claim 7 , wherein the portion of the metal-containing compound layer is over the bottom electrode.
9. The memory device of claim 4 , wherein a bottom surface of the second spacer is over the top surface of the bottom electrode.
10. A memory device, comprising:
a bottom electrode;
a resistance switching element over the bottom electrode;
a top electrode over the resistance switching element; and
a metal-containing compound layer extending from the bottom electrode to the top electrode, wherein the metal-containing compound layer has a portion extending substantially along a top surface of the bottom electrode.
11. The memory device of claim 10 , wherein the portion of the metal-containing compound layer extends from an edge of the top surface of the bottom electrode.
12. The memory device of claim 10 , further comprising a conductor connected to the top electrode, wherein the conductor is at least partially in the metal-containing compound layer.
13. The memory device of claim 10 , further comprising a spacer separating the metal-containing compound layer from the resistance switching element.
14. The memory device of claim 10 , wherein the metal-containing compound layer has a portion on a sidewall of the resistance switching element.
15. A semiconductor device, comprising:
a substrate;
a plurality of bottom electrodes over the substrate;
a plurality of resistance switching elements over the bottom electrodes, respectively;
a plurality of top electrodes over the resistance switching elements, respectively;
a plurality of metal-containing compound layers surrounding the resistance switching elements, respectively;
a plurality of first interlayer dielectric layers surrounding the resistance switching elements, respectively;
a second interlayer dielectric layer separating the first interlayer dielectric layers from each other; and
a plurality of conductors at least partially in the first interlayer dielectric layers and connected to the top electrodes, respectively, wherein the conductors are at least partially in the metal-containing compound layers, respectively.
16. The semiconductor device of claim 15 , wherein the second interlayer dielectric layer is at least partially between the metal-containing compound layers.
17. The semiconductor device of claim 15 , wherein the second interlayer dielectric layer is at least partially between the bottom electrodes.
18. The semiconductor device of claim 15 , wherein the second interlayer dielectric layer has a first interface with one of the bottom electrodes and a second interface with one of the metal-containing compound layers over said one of the bottom electrodes, wherein the first interface is connected with the second interface.
19. The semiconductor device of claim 15 , wherein the conductors are at least partially in the second interlayer dielectric layer.
20. The semiconductor device of claim 15 , wherein a bottom surface of the first interlayer dielectric layers is over a top surface of the bottom electrodes.