IP Library Granted Patent US 12,290,003
Granted Patent B2
US 12,290,003 · App. 18/079,043 · Granted Apr 29, 2025

Conductive structure connection with interconnect structure

Inventors: Sheng-Chau Chen (Tainan, TW); Cheng-Tai Hsiao (Tainan, TW); Cheng-Yuan Tsai (Chu-Pei, TW); Hsun-Chung Kuang (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10N50/80H10B61/00H10N50/01
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Quick Facts
Patent No.
US 12,290,003
App. No.
18/079,043
Granted
Apr 29, 2025
Kind
B2
Abstract

Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body. A sidewall spacer is disposed on the sidewall of the conductive structure.

Claims (38)

1. A semiconductor structure, comprising:

a conductive structure over a semiconductor substrate;

a first dielectric layer over the conductive structure;

a second dielectric layer over the first dielectric layer;

an interconnect structure over the conductive structure and disposed in the first and second dielectric layers, wherein the interconnect structure has a protrusion in contact with a sidewall of the conductive structure, wherein the interconnect structure comprises an interconnect liner surrounding a conductive interconnect body, wherein a bottom surface of the protrusion is flat and below a top surface of the conductive structure; and

a sidewall spacer disposed on the sidewall of the conductive structure.

2. The semiconductor structure of claim 1 , further comprising:

a liner layer overlying the semiconductor substrate, wherein the liner layer encloses the sidewall spacer.

3. The semiconductor structure of claim 2 , wherein the sidewall spacer has a bottom surface aligned with a bottom surface of the liner layer.

4. The semiconductor structure of claim 2 , wherein the sidewall spacer and the liner layer directly contact the bottom surface of the protrusion.

5. The semiconductor structure of claim 2 , wherein a top surface of the liner layer is disposed above the bottom surface of the protrusion of the interconnect structure.

6. The semiconductor structure of claim 2 , wherein the sidewall spacer comprises a first material and the liner layer comprises a second material different than the first material.

7. The semiconductor structure of claim 1 , wherein a width of the bottom surface of the protrusion is greater than a width of a top surface of the sidewall spacer.

8. The semiconductor structure of claim 1 , wherein the sidewall spacer is spaced laterally between sidewalls of the protrusion of the interconnect structure.

9. A semiconductor device, comprising:

a conductive structure over a semiconductor substrate;

a dielectric structure over the conductive structure;

an interconnect structure disposed over the conductive structure, wherein the interconnect structure comprises a protrusion extending along a sidewall of the conductive structure;

a sidewall spacer disposed along the sidewall of the conductive structure; and

a liner layer over the semiconductor substrate and along the sidewall spacer, wherein the liner layer and the protrusion of the interconnect structure enclose the sidewall spacer.

10. The semiconductor device of claim 9 , wherein the protrusion continuously extends along a portion of the sidewall of the conductive structure between a top surface of the conductive structure and a top surface of the sidewall spacer.

11. The semiconductor device of claim 9 , wherein the dielectric structure overlies the liner layer, wherein the dielectric structure comprises a first dielectric layer over the conductive structure, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise different materials from one another, and wherein the first, second, and third dielectric layers contact a sidewall of the interconnect structure.

12. The semiconductor device of claim 9 , wherein a width of the interconnect structure continuously decreases from a top surface of the interconnect structure in a direction towards the semiconductor substrate.

13. The semiconductor device of claim 9 , wherein the sidewall spacer and the liner layer abut a bottom surface of the protrusion at a point lower than a top surface of the conductive structure.

14. The semiconductor device of claim 13 , wherein an outer sidewall of the sidewall spacer contacts an inner sidewall of the liner layer at an interface, wherein the protrusion continuously abuts the interface.

15. The semiconductor device of claim 9 , wherein the interconnect structure comprises a liner surrounding a metal structure.

16. A semiconductor device, comprising:

a conductive structure over a semiconductor substrate;

a first dielectric layer over the conductive structure;

a second dielectric layer over the first dielectric layer;

a third dielectric layer over the second dielectric layer;

an interconnect structure over the conductive structure, wherein the interconnect structure comprises an interconnect liner surrounding a conductive interconnect body, wherein the interconnect structure comprises a conductive segment in contact with a sidewall of the conductive structure;

a sidewall spacer disposed along the sidewall of the conductive structure; and

a liner layer over the semiconductor substrate and covering the sidewall spacer, wherein the liner layer encloses the sidewall spacer, and wherein the sidewall spacer and liner layer contact a bottom surface of the conductive segment at a point below a top surface of the conductive structure.

17. The semiconductor device of claim 16 , wherein a top surface of the sidewall spacer is enclosed by the conductive segment, and wherein a top surface of the liner layer is above the bottom surface of the conductive segment.

18. The semiconductor device of claim 16 , wherein the conductive segment continuously vertically extends from a top surface of the sidewall spacer to the top surface of the conductive structure.

19. The semiconductor device of claim 16 , wherein the first, second, and third dielectric layers contact a sidewall of the interconnect structure, wherein the first dielectric layer comprises a first material and the second dielectric layer comprises a second material different from the first material.

20. The semiconductor device of claim 16 , wherein an outer sidewall of the conductive segment is straight and slanted by a non-zero angle.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2022
From: CHEN, SHENG-CHAU; HSIAO, CHENG-TAI; TSAI, CHENG-YUAN; KUANG, HSUN-CHUNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 062049/0655 →
Continuity (5)
Continuation 17528574 · Nov 17, 2021
Continuation 16732385 · Jan 2, 2020
Continuation 16051759 · Aug 1, 2018
Provisional Application 62691244 · Jun 28, 2018
Related Publication 20230103309A1 · Apr 6, 2023
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