Semiconductor structure and method of forming the same

1. A semiconductor structure, comprising:

a logic region;

a memory region adjacent to the logic region, the memory region comprises:

a N th metal layer;

a bottom electrode over the N th metal layer;

a magnetic tunneling junction (MTJ) layer over the bottom electrode;

a top electrode over the MTJ layer; and

a (N+1) th metal layer over the top electrode;

wherein the top electrode comprises:

an upper portion, interfacing with a bottom surface of the (N+1) th metal layer, the upper portion being composed of material having a first oxidation rate; and

a lower portion, interfacing with a top surface of the MTJ layer, the lower portion being composed of material having a second oxidation rate, the upper portion being laterally narrower than the lower portion;

wherein the first oxidation rate is slower than the second oxidation rate, and

wherein N is an integer greater than or equal to 1.

2. The semiconductor structure of claim 1 , wherein the upper portion of the top electrode comprises TiN.

3. The semiconductor structure of claim 1 , wherein the lower portion of the top electrode is composed of Tantalum or Tantalum derivatives.

4. The semiconductor structure of claim 1 , wherein the N th metal layer in the logic region comprises N th metal line and N th metal via.

5. The semiconductor structure of claim 1 , wherein the N th metal layer and the (N+1) th metal layer comprises copper.

6. The semiconductor structure of claim 1 , wherein the bottom electrode and the top electrode comprises same material.

7. The semiconductor structure of claim 1 , wherein the memory region is an embedded MRAM.

8. A semiconductor structure, comprising:

a logic periphery, comprising:

a transistor region;

a N th metal over the transistor region; and

a (N+1) th metal over the N th metal; and

a magnetic random access memory (MRAM) cell, comprising:

the (N+1) th metal; and

a top electrode in contact with the (N+1) th metal,

wherein the top electrode comprises:

TiN at an interface between the top electrode and the (N+1) th metal; and

a tantalum layer or a tantalum derivative layer under the TiN, the TiN layer being laterally narrower than the tantalum layer or the tantalum derivative layer.

wherein N is an integer greater than or equal to 1.

9. The semiconductor structure of claim 8 , wherein the MRAM cell further comprises a magnetic tunneling junction (MTJ) layer.

10. The semiconductor structure of claim 8 , wherein the MRAM cell further comprises a bottom electrode having a same material with the top electrode.

11. The semiconductor structure of claim 9 , wherein the tantalum layer or the tantalum derivative layer is in contact with the MTJ layer.

12. The semiconductor structure of claim 8 , wherein the N th metal comprises an N th metal line and an N th metal via.

13. The semiconductor structure of claim 12 , wherein the (N+1) th metal line and the N th metal via are surrounded by low-k dielectric in the logic periphery.

14. The semiconductor structure of claim 10 , wherein the MTJ layer is surrounded by a nitride layer.

15. The semiconductor structure of claim 10 , wherein the (N+1) th metal is partially surrounded by SiC in the MRAM cell.

16. A method for manufacturing a semiconductor structure, the method comprising:

forming an N th metal in a memory region and in a logic region;

forming a magnetic tunneling junction (MTJ) layer over the N th metal;

forming a top electrode over the MTJ layer in the memory region, comprising:

forming a lower top electrode layer interfacing with a top surface of the MTJ layer, the lower top electrode layer being composed of material having a first oxidation rate;

forming an upper top electrode layer over the lower top electrode layer, the upper top electrode layer being composed of material having a second oxidation rate, wherein the first oxidation rate is faster than the second oxidation rate; and

forming a mask layer over the upper top electrode layer; and

patterning the lower top electrode layer, the upper top electrode layer, and the MTJ layer via the mask layer in a single operation; and

forming a (N+1) th metal above the N th metal in the logic region and the memory region.

17. The method of claim 16 , wherein the forming the (N+1) th metal comprises forming an N th metal via and an (N+1) th metal line in the logic region.

18. The method of claim 17 , wherein the forming the (N+1) th metal comprises a Dual Damascene operation.

19. The method of claim 16 , wherein the forming the (N+1) th metal above the N th metal in the memory region comprises electroplating copper over a TiN surface.

20. The method of claim 16 , wherein the upper portion of the top electrode interfaces with a lower surface of the (N+1) th metal in the memory region.