Etch stop layer for memory device formation

1. A method of forming an integrated chip, comprising:

forming a memory device over a substrate;

forming an etch stop layer over the memory device;

forming an inter-level dielectric (ILD) layer over the etch stop layer and laterally surrounding the memory device;

performing a patterning process to define a first trench that exposes an upper surface and a sidewall of the etch stop layer;

performing a removal process, after performing the patterning process, to remove an exposed part of the etch stop layer; and

forming a conductive material within the first trench after performing the removal process.

2. The method of claim 1 , wherein the removal process comprises a wet cleaning process or a wet etching process.

3. The method of claim 1 , further comprising:

performing a first patterning process on the ILD layer to form a first intermediate trench over the memory device, wherein the first intermediate trench is separated from the etch stop layer by the ILD layer; and

performing the patterning process on the ILD layer to increase a depth of the first trench and to define the first trench.

4. The method of claim 3 , further comprising:

forming a via hole and an overlying second trench within the ILD layer, wherein the second trench and the via hole expose a second part of the etch stop layer prior to performing the second patterning process.

5. The method of claim 4 , wherein the via hole exposes a second upper surface of the etch stop layer that is laterally outside of the memory device.

6. The method of claim 4 , further comprising:

performing a second removal process to remove the second part of the etch stop layer prior to performing the removal process.

7. The method of claim 6 , wherein the second removal process comprises a wet cleaning process or a wet etching process.

8. The method of claim 1 , wherein the sidewall and the upper surface of the etch stop layer define the first trench.

9. The method of claim 1 ,

wherein the etch stop layer has a first upper surface along a first side of the memory device and a second upper surface along a second side of the memory device opposing the first side after performing the removal process; and

wherein the first upper surface and the second upper surface are at different heights over the substrate.

10. A method of forming an integrated chip, comprising:

forming a memory device over one or more lower inter-level dielectric (ILD) layers on a substrate, wherein the memory device comprises a data storage structure disposed between a bottom electrode and a top electrode;

forming an etch stop layer over the top electrode, wherein the etch stop layer comprises a metal oxide or a metal nitride;

forming an upper ILD layer over the etch stop layer and laterally surrounding the memory device;

forming a recess within the upper ILD layer, wherein the recess extends from a top of the upper ILD layer to the etch stop layer;

removing an exposed part of the etch stop layer; and

forming an upper interconnect wire within the recess.

11. The method of claim 10 ,

wherein the upper ILD layer has a horizontally extending surface that is directly below the upper interconnect wire and laterally outside of a top surface of the memory device; and

wherein the etch stop layer has a top surface that is recessed below the horizontally extending surface.

12. The method of claim 10 , further comprising:

forming a lower insulating structure over the one or more lower ILD layers;

forming a bottom electrode via within the lower insulating structure, wherein the bottom electrode is formed over the bottom electrode via; and

forming a via hole defined by sidewalls of the upper ILD layer, the etch stop layer, and the lower insulating structure.

13. The method of claim 12 , wherein the sidewalls of the etch stop layer defining the via hole are laterally set back from the sidewalls of the lower insulating structure defining the via hole by a non-zero distance.

14. The method of claim 10 , wherein a first etchant is used to define the recess within the upper ILD layer and a wet cleaning chemical is used to remove the etch stop layer, the first etchant different than the wet cleaning chemical.

15. An integrated chip, comprising:

a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate;

one or more sidewall spacers arranged along opposing sides of the memory device;

an upper ILD layer laterally surrounding the memory device;

an etch stop layer disposed on a sidewall of the one or more sidewall spacers and over an upper surface of the one or more lower ILD layers, wherein the etch stop layer has a topmost surface that is vertically below both a top of the memory device and a topmost surface of the one or more sidewall spacers; and

an upper interconnect wire contacting sidewalls of the memory device above the etch stop layer.

16. The memory device of claim 15 , further comprising:

a lower insulating structure disposed over the one or more lower ILD layers;

a bottom electrode via extending through the lower insulating structure between the lower interconnect and the memory device; and

an upper insulating structure separating the lower insulating structure from the upper ILD layer.

17. The memory device of claim 16 , wherein the upper interconnect wire has a first lower surface resting on the topmost surface of the etch stop layer and a second lower surface resting on the topmost surface of the one or more sidewall spacers, the second lower surface vertically above the first lower surface.

18. The memory device of claim 15 ,

wherein the upper ILD layer has a horizontally extending surface that is directly below the upper interconnect wire and laterally outside of the memory device; and

wherein the topmost surface of the etch stop layer is recessed a non-zero distance below the horizontally extending surface.

19. The memory device of claim 15 , wherein the etch stop layer has a first upper surface along a first side of the memory device and a second upper surface along a second side of the memory device opposing the first side, the first upper surface and the second upper surface being disposed at different heights over the substrate.

20. The memory device of claim 15 , wherein the etch stop layer comprises a metal oxide or a metal nitride.