Nanosheet channel-to-source and drain isolation
A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
1. A semiconductor integrated circuit comprising:
a nanosheet stack comprising:
a first semiconductor layer;
a second semiconductor layer, the second semiconductor layer disposed above and separated from the first semiconductor layer;
a first pair of inner spacers underpinning opposite sides of the first semiconductor layer; and
a second pair of inner spacers between the first semiconductor layer and the second semiconductor layer, the second pair of inner spacers underpinning opposite sides of the second semiconductor layer;
a first source-drain region on a first side of the nanosheet stack, the first source-drain region contacting (i) the first semiconductor layer, (ii) the second semiconductor layer, and (iii) an inter-source-drain dielectric region on a first side of the inter-source-drain dielectric region;
a second source-drain region on a second side of the inter-source-drain dielectric region opposite the first side of the inter-source-drain dielectric region, the second source-drain region contacting the inter-source-drain dielectric region; and
a gate structure comprising a high-k gate dielectric layer and a work-function metal layer on the first and second semiconductor layers and between the first and second semiconductor layers.
2. The semiconductor integrated circuit of claim 1 , wherein:
the first semiconductor layer comprises a silicon layer; and
the second semiconductor layer comprises a silicon layer.
3. The semiconductor integrated circuit of claim 1 , wherein:
the first pair of inner spacers comprises silicon and nitrogen; and
the second pair of inner spacers comprises silicon and nitrogen.
4. The semiconductor integrated circuit of claim 1 , wherein:
the first pair of inner spacer comprises a low-k material; and
the second pair of inner spacer comprises a low-k material.
5. The semiconductor integrated circuit of claim 4 , wherein the low-k material comprises silicon and carbon.
6. The semiconductor integrated circuit of claim 4 , wherein the low-k material comprises silicon and boron.
7. The semiconductor integrated circuit of claim 4 , wherein the low-k material comprises silicon, boron, carbon, and nitrogen.
8. The semiconductor integrated circuit of claim 1 , wherein the inter-source-drain dielectric region comprises a first dielectric material laterally recessed at a first vertical distance from a top surface of a substrate, wherein the first vertical distance is substantially equal to a second vertical distance from the top surface of the substrate to the first semiconductor layer.
9. The semiconductor integrated circuit of claim 8 , wherein the inter-source-drain dielectric region comprises a second dielectric material filling at least in part a recess in the first dielectric material.
10. The semiconductor integrated circuit of claim 9 , wherein the second dielectric material filling at least in part the recess comprises a same material as the first and second pairs of inner spacers.
11. A semiconductor integrated circuit comprising:
a first nanosheet fin extending in a first direction and comprising at least a first semiconductor nanosheet and a second semiconductor nanosheet, the first nanosheet fin further comprising:
a first pair of inner spacers disposed under and contacting the first semiconductor nanosheet; and
a second pair of inner spacers (i) disposed above and contacting the first semiconductor nanosheet and (ii) disposed under and contacting the second semiconductor nanosheet;
a second nanosheet fin adjacent to the first nanosheet fin and extending in the first direction, the second nanosheet fin comprising at least a third semiconductor nanosheet and a fourth semiconductor nanosheet, the second nanosheet fin further comprising:
a third pair of inner spacers disposed under and contacting the third semiconductor nanosheet; and
a fourth pair of inner spacers (i) disposed above and contacting the third semiconductor nanosheet and (ii) disposed under and contacting the fourth semiconductor nanosheet;
a gate structure extending in a second direction substantially perpendicular to the first direction, the gate structure disposed over and between the first and second nanosheet fins, including over and between the first, second, third, and fourth semiconductor nanosheets, the gate structure comprising outer spacers in regions above the first and second nanosheet fins;
an inter-source-drain dielectric region extending in the second direction;
a first source-drain region extending in the second direction on a first side of the inter-source-drain dielectric region and contacting the inter-source-drain dielectric region, the first source-drain region contacting (i) the first, second, third, and fourth semiconductor nanosheets and (ii) the first, second, third, and fourth pairs of inner spacers; and
a second source-drain region extending in the second direction on a second side of the inter-source-drain dielectric region opposite the first side of the inter-source-drain dielectric region, the second source-drain region contacting the inter-source-drain dielectric region.
12. The semiconductor integrated circuit of claim 11 , wherein the inter-source-drain dielectric region comprises a first dielectric material laterally recessed at a first vertical distance from a top surface of a substrate, wherein the first vertical distance is substantially equal to a second vertical distance from the top surface of the substrate to a first semiconductor layer.
13. The semiconductor integrated circuit of claim 12 , wherein the inter-source-drain dielectric region comprises a second dielectric material filling at least in part a recess in the first dielectric material.
14. The semiconductor integrated circuit of claim 13 , wherein the second dielectric material filling at least in part the recess comprises a same material as the first, second, third, and fourth pairs of inner spacers.
15. The semiconductor integrated circuit of claim 11 , wherein the first, second, third, and fourth pairs of inner spacers comprise silicon and carbon.
16. The semiconductor integrated circuit of claim 11 , wherein the first, second, third, and fourth pairs of inner spacers comprise silicon and boron.
17. The semiconductor integrated circuit of claim 11 , wherein the first, second, third, and fourth pairs of inner spacers comprise silicon, boron, carbon, and nitrogen.
18. The semiconductor integrated circuit of claim 1 , wherein the inter-source-drain dielectric region is a first dielectric region and the semiconductor integrated circuit further comprises:
spacers disposed on an upper portion of the gate structure; and
a second dielectric region disposed over the first dielectric region, wherein the second dielectric region is laterally adjacent to the spacers, and the first dielectric region and the second dielectric region comprise different materials.
19. The semiconductor integrated circuit of claim 18 , wherein an interface between the first dielectric region and the second dielectric regions is disposed above the first and second source-drain regions.
20. The semiconductor integrated circuit of claim 11 , wherein the inter-source-drain dielectric region is a first dielectric region and the semiconductor integrated circuit further comprises:
spacers disposed on an upper portion of the gate structure; and
a second dielectric region disposed over the first dielectric region, wherein the second dielectric region is laterally adjacent to the spacers, and the first dielectric region and the second dielectric region comprise different materials.
21. The semiconductor integrated circuit of claim 20 , wherein an interface between the first dielectric region and the second dielectric regions is disposed above the first and second source-drain regions.