IP Library › Granted Patent US 12,389,815
Granted Patent B2
US 12,389,815 · App. 17/347,898 · Granted Aug 12, 2025

Filament-metal oxide channel exchange resistive memory device

Inventors: Laura Bégon-Lours (Paris, FR); Valeria Bragaglia (Zurich, CH); Jean Fompeyrine (Waedenswil, CH); Antonio La Porta (Kilchberg, CH); Mattia Halter (Zurich, CH)
Assignee: International Business Machines Corporation
H10N70/8833H10B63/80H10N70/028H10N70/063H10N70/068H10N70/841
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Quick Facts
Patent No.
US 12,389,815
App. No.
17/347,898
Granted
Aug 12, 2025
Kind
B2
Abstract

An approach to provide a semiconductor structure for a resistive switch device. The resistive switch device includes a bottom electrode, a dielectric material over the bottom electrode, and a metal oxide material on a portion of the dielectric material connecting to a portion of a top electrode where the metal oxide material has a controlled volume. Additionally, the approach includes a plurality of the resistive switch devices in a crossbar. The crossbar array includes the plurality of resistive switch devices on more than one bottom electrode and at least one top electrode connecting to the plurality of resistive switch devices.

Claims (44)

1. A resistive switch device, the resistive switch device comprising:

a bottom electrode;

a dielectric material over the bottom electrode, wherein:

a bottom surface of the dielectric material contacts a top surface of the bottom electrode; and

the bottom surface of the dielectric material has a surface area smaller than the top surface of the bottom electrode; and

a metal oxide material on a portion of the dielectric material connecting to a portion of a top electrode.

2. The resistive switch device of claim 1 , wherein the metal oxide material on the portion of the dielectric material has a controlled area.

3. The resistive switch device of claim 1 , wherein the metal oxide on the portion of the dielectric material has a volume that is reduced to increase a resistance of the metal oxide material in the resistive switch device.

4. The resistive switch device of claim 1 , wherein the metal oxide material on the portion of the dielectric material provides a largest portion of a total resistance of a resistive random-access memory.

5. The resistive switch device of claim 3 , wherein the volume of the metal oxide material is determined by an area of the metal oxide on the portion of the dielectric material and a controlled thickness of the metal oxide material.

6. The resistive switch device of claim 1 , wherein the metal oxide material on the portion of the dielectric material has a controlled resistivity.

7. The resistive switch device of claim 6 , wherein the controlled resistivity of the metal oxide material is determined, at least in part, by one or more post-oxidation reduction processes.

8. The resistive switch device of claim 7 , wherein the one or more post-oxidation reduction processes include one or more of a reducing bake process, a low temperature bake, and an anneal.

9. The resistive switch device of claim 6 , wherein the controlled resistivity of the metal oxide material is determined, at least in part, by a volume of the metal oxide material.

10. The resistive switch device of claim 1 , wherein the resistive switch device is in an OFF state when the metal oxide material has a high resistance and when a filament in the dielectric material over the bottom electrode is thick.

11. The resistive switch device of claim 10 , wherein the metal oxide material has the high resistance with a high oxygen content in the metal oxide material.

12. The resistive switch device of claim 10 , wherein the resistive switch is in an SET state when the metal oxide material has a low resistance and when the filament in the dielectric material over the bottom electrode is thin.

13. A crossbar array of resistive switch devices, the crossbar array comprising:

a first resistive switch device comprising:

a first plurality of metal oxide elements on a first dielectric material layer; and

the first dielectric material layer on a first bottom electrode;

a second resistive switch device comprising:

a second plurality of metal oxide elements on a second dielectric material layer; and

the second dielectric material layer on a second bottom electrode; and

a top electrode connecting the first resistive switch device to the second resistive switch device.

14. The crossbar array of claim 13 , further comprising a passivation surrounding each of the first resistive switch device and the second of resistive switch device.

15. The crossbar array of claim 13 , wherein:

each of the metal oxide elements has a controlled thickness and a controlled electrical resistance; and

the first dielectric material layer is capable of forming a conductive filament connecting the first bottom electrode to a metal oxide element of the first plurality of metal oxide elements.

16. A method of forming a resistive switch device, the method comprising:

forming a bottom electrode in a metal layer;

depositing a layer of a dielectric material, wherein the dielectric material is capable of generating a conduction path with an applied electric field;

selectively etching the dielectric material such that a bottom surface of the dielectric material contacting a top surface of the bottom electrode has a surface area smaller than the top surface of the bottom electrode;

depositing a passivation material;

selectively etching the passivation material to expose a portion of the dielectric material;

depositing a metal layer on the exposed portion of the dielectric material and over the passivation material;

oxidizing the metal layer forming a metal oxide material;

reducing the metal oxide material; and

performing a chemical-mechanical polish to remove excess metal oxide material; and

forming a top electrode.

17. The method of claim 16 , wherein selectively etching the passivation material to expose the portion of the dielectric material determines, at least in part, a resistivity of the metal oxide material in a resistive switch device.

18. The method of claim 16 , wherein reducing the metal oxide material determines, at least in part, the resistivity of the metal oxide material in a resistive switch device.

19. The method of claim 16 , wherein reducing the metal oxide material includes a process selected from the group consisting of: a bake in a low hydrogen reducing environment, a bake in a medium hydrogen reducing environment, a bake in a high hydrogen reducing environment, a bake without the reducing environment, and an anneal.

20. The method of claim 16 , wherein the metal oxide material is a tungsten oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2021
From: BÉGON-LOURS, LAURA; BRAGAGLIA, VALERIA; FOMPEYRINE, JEAN; LA PORTA, ANTONIO; HALTER, MATTIA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 056547/0286 →
Continuity (1)
Related Publication 20220399497A1 · Dec 15, 2022
References Cited (26)
US 8787066B2 · Wang · 2014 [cited by applicant]
US 10312441B1 · Fompeyrine et al. · 2019 [cited by applicant]
US 10516108B2 · Fompeyrine · 2019 [cited by applicant]
US 10777608B2 · Lu · 2020 [cited by applicant]
US 11462585B2 · Lu · 2022 [cited by examiner]
US 20170365641A1 · Bedau · 2017 [cited by applicant]
US 20190288195A1 · Lu · 2019 [cited by applicant]
CN 104361908A · 2015 [cited by applicant]
CN 106953007A · 2017 [cited by applicant]
CN 108470827A · 2018 [cited by applicant]
Acharya, et al., “Epitaxial Brownmillerite Oxide Thin Films for Reliable Switching Memory”, ACS Applied Materials and Interfaces, downloaded from the internet on Feb. 25, 2021, 10 pps., Korea, <https://pubs.acs.org/doi/… [cited by applicant]
Beck, et al., “Reproducible switching effect in thin oxide films for memory applications”, Applied Physics Letters, Jun. 28, 2000, 4 pps., <https://doi.org/10.1063/1.126902>. [cited by applicant]
Chang, et al., “Synaptic behaviors and modeling of a metal oxide memristive device”, Applied Physics A Materials Science & Processing, Feb. 5, 2011, 7 pps. [cited by applicant]
Chien, et al., “A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM”, Applied Physics A Materials Science & Processing, 2011, 7 pps. [cited by applicant]
Dirkmann, et al., “The role of ion transport phenomena in memristive double barrier devices”, Scientific Reports, Oct. 20, 2016, 12 pps., <https://www.nature.com/articles/srep35686>. [cited by applicant]
Jo, et al., “Nanoscale Memristor Device as Synapse in Neuromorphic Systems”, Nano Letters, 2010, 5 pps., Department of Electrical Engineering and Computer Science, University of Michigan, Michigan, <https://pubs.acs.org… [cited by applicant]
Tambunan, et al., “Resistance switching in epitaxial SrCoOx thin films”, Applied Physics Letters, Aug. 14, 2014, 6 pps., <https://doi.org/10.1063/1.4893323>. [cited by applicant]
Waser, et al., “Redox-Based Resistive Switching Memories—Nanoionic Mechanisms, Prospects, and Challenges”, Advanced Materials, 2009, 32 pps., Germany. [cited by applicant]
Yang, et al., “Memristive devices for computing”, Nature Nanotechnology, Dec. 27, 2021, 12 pps., <https://www.nature.com/articles/nnano.2012.240>. [cited by applicant]
Garbin, et al., GrenoblHfO2 Based OxRAM Devices as Synapses for Convolutional Neural Networks, IEEE Transactions on Electron Devices, Aug. 2015, vol. 62, Issue: 8, pp. 2494-2501. [cited by applicant]
Gokmen, et al., Acceleration of Deep Neural Network Training with Resistive Cross-Point Devices: Design Considerations, Frontiers in Neuroscience, Jul. 21, 2016, vol. 10, Article 333, 13 pages. [cited by applicant]
Gong, et al., Signal and Noise Extraction From Analog Memory Elements for Neuromorphic Computing, Nature Communications, May 29, 2018, 8 pages. [cited by applicant]
Hansen, K., A Reduced-Dimensional Model for Near-Wall Transport In Cardiovascular Flows, Biomechanics and Modeling in Mechanobiology, Aug. 23, 2015, vol. 15, 26 pages. [cited by applicant]
Ielmini, et al., In-Memory Computing with Resistive Switching Devices, Nature electronics, Jul. 13, 2018, vol. 1, No. 6, pp. 333-343. [cited by applicant]
Tang, et al., ECRAM as Scalable Synaptic Cell for High-Speed, Low-Power Neuromorphic Computing, IEEE International Electron Devices Meeting (IEDM), Dec. 1-5, 2018, pp. 13.1.1-13.1.4. [cited by applicant]
Wang, et al., 3D Synaptic Architecture With Ultralow Sub-10 Fj Energy Per Spike For Neuromorphic Computation, Electron Devices Meeting, 1988. IEDM '88., Feb. 2015, 28 pages. [cited by applicant]