Hetero-plane data storage structures for non-volatile memory

1. A flash memory die of a data storage system, the flash memory die comprising:

a first subset of one or more planes, wherein each plane of the first subset includes a plurality of blocks of flash memory cells connected to (i) a first number of word line layers and (ii) a plurality of bit lines having a first length;

a second subset of one or more planes, wherein each plane of the second subset includes a plurality of blocks of flash memory cells connected to (ii) a second number of word line layers less than the first number of word line layers and (ii) a plurality of bit lines having a second length shorter than the first length;

first peripheral circuitry implemented underneath the first subset of planes and including:

first sense amplifier circuitry connected to the first subset of planes,

first peripheral control circuitry connected to the first subset of planes; and

second peripheral control circuitry connected to the second subset of planes; and

second peripheral circuitry implemented underneath the second subset of planes and including

second sense amplifier circuitry connected to the second subset of planes.

2. The flash memory die of claim 1 , wherein:

the first peripheral circuitry is arranged in a complementary metal-oxide-semiconductor (CMOS) under array (CUA) architecture under the plurality of blocks of flash memory cells of the first subset of planes; and

the second peripheral circuitry is arranged in a CUA architecture under the plurality of blocks of flash memory cells of the second subset of planes.

3. The flash memory die of claim 1 , wherein:

the first subset of planes includes four planes arranged in two rows of two planes each; and

the second subset of planes includes four planes arranged in one row.

4. The flash memory die of claim 1 , further comprising:

third peripheral circuitry located adjacent to the first subset of planes or the second subset of planes and including bonding pads configured to connect to an interface channel between the flash memory die and a storage controller of the data storage system.

5. The flash memory die of claim 4 , wherein the third peripheral circuitry is arranged in a CMOS next to array (CNA) architecture adjacent to the plurality of blocks of flash memory cells of the first or second subset of planes.

6. The flash memory die of claim 4 , wherein the first subset of planes is located between the second subset of planes and the third peripheral circuitry.

7. The flash memory die of claim 4 , wherein the second subset of planes is located between the first subset of planes and the third peripheral circuitry.

8. The flash memory die of claim 1 , wherein:

each of the first subset of planes includes a first number of blocks of flash memory cells; and

each of the second subset of planes includes a second number of blocks of flash memory cells less than the first number of blocks of flash memory cells.

9. The flash memory die of claim 1 , wherein:

each of the first subset of planes has a first vertical height extending away from the first peripheral circuitry; and

each of the second subset of planes has a second vertical height shorter than the first vertical height extending away from the second peripheral circuitry.

10. The flash memory die of claim 1 , wherein:

each of the first subset of planes is optimized for cost scalability; and

each of the second subset of planes is optimized for read performance.

11. The flash memory die of claim 1 , wherein:

each of the first subset of planes includes at least 96 word line layers; and

each of the second subset of planes is associated with a read latency of 3 microseconds or less.

12. The flash memory die of claim 1 , wherein:

the flash memory cells in each of the first subset of planes are configured to store at least three bits of data per cell; and

the flash memory cells in each of the second subset of planes are configured to store one or two bits of data per cell.

13. The flash memory die of claim 1 , wherein the first peripheral control circuitry and the second peripheral control circuitry include voltage regulators, charge pumps, page buffers, timing circuits, and level shifters.

14. The flash memory die of claim 1 , wherein the first subset of planes, the second subset of planes, the first peripheral circuitry, and the second peripheral circuitry are implemented in a single wafer.

15. The flash memory die of claim 1 , wherein:

the first subset of planes and the second subset of planes are implemented in a first wafer;

the first peripheral circuitry and the second peripheral circuitry are implemented in a second wafer; and

the first wafer and the second wafer are bonded together.

16. A flash memory die of a data storage system, the flash memory die comprising:

one or more triple-level-cell (TLC) or quad-level-cell (QLC) planes, wherein each of the one or more TLC or QLC planes includes a first plurality of blocks of flash memory cells;

one or more low latency flash (LLF) planes, wherein each of the one or more LLF planes includes a second plurality of blocks, fewer than the first plurality of blocks, of flash memory cells;

a first complementary metal-oxide-semiconductor (CMOS) under array (CUA) region of peripheral circuitry located underneath the one or more TLC or QLC planes;

a second CUA region of peripheral circuitry located underneath the one or more LLF planes;

first sense amplifier circuitry connected to the one or more TLC or QLC planes and implemented in the first CUA region;

first peripheral control circuitry connected to the one or more TLC or QLC planes and implemented in the first CUA region;

second sense amplifier circuitry connected to the one or more LLF planes and implemented in the second CUA region; and

second peripheral control circuitry connected to the one or more LLF planes and implemented in the first CUA region and not in the second CUA region.

17. The flash memory die of claim 16 , wherein the first CUA region and the second CUA region do not overlap.

18. The flash memory die of claim 16 , at least two TLC or QLC planes of the one or more TLC or QLC planes are adjacent to at least two LLF planes of the one or more LLF planes with no CMOS next to array (CNA) peripheral circuitry between the at least two TLC or QLC planes and the at least two LLF planes.

19. The flash memory die of claim 16 , further comprising a CNA region of peripheral circuitry adjacent to the first CUA region or the second CUA region and including bonding pads configured to connect to an interface channel between the flash memory die and a storage controller of the data storage system.

20. A flash memory die of a data storage system, the flash memory die comprising:

means for storing data in a first subset of one or more planes, wherein each plane of the first subset includes a plurality of blocks of flash memory cells connected to (i) a first number of word line layers and (ii) a plurality of bit lines having a first length;

means for storing data in a second subset of one or more planes, wherein each plane of the second subset includes a plurality of blocks of flash memory cells connected to (ii) a second number of word line layers less than the first number of word line layers and (ii) a plurality of bit lines having a second length shorter than the first length;

means for processing stored data in first peripheral circuitry implemented underneath the first subset of planes and including:

first sensing means connected to the first subset of planes,

first control means connected to the first subset of planes; and

second control means connected to the second subset of planes; and

means for processing stored data in second peripheral circuitry implemented underneath the second subset of planes and including second sensing means connected to the second subset of planes.