Multigate devices with varying channel layers
Multigate devices and methods for fabricating such are disclosed herein. An exemplary multigate device includes a first FET disposed in a first region; and a second FET disposed in a second region of a substrate. The first FET includes first channel layers disposed over the substrate, and a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers. The second FET includes second channel layers disposed over the substrate, and a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers. A number of the first channel layers is greater than a number of the second channel layers. A bottommost one of the first channel layers is below a bottommost one of the second channel layers.
1 . A multigate device comprising:
a backside dielectric layer having a first region and a second region;
a first field effect transistor (FET) disposed in the first region, wherein the first FET includes:
first channel layers disposed over the backside dielectric layer,
a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers,
first source/drain features interposed by the first gate stack and extended to contact the each of the first channel layers, and
a first dielectric feature disposed below and interfacing a bottom surface of one of the first source/drain features; and
a second FET disposed in the second region, wherein the second FET includes:
second channel layers disposed over the backside dielectric layer,
a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers,
second source/drain features interposed by the second gate stack and extended to contact the each of the second channel layers,
silicon features disposed on sidewalls of the second source/drain features such that each of the silicon features is disposed between one of the second source/drain features and the backside dielectric layer, and
a second dielectric feature disposed below and interfacing a bottom surface of one of the second source/drain features,
wherein a number of the first channel layers is greater than a number of the second channel layers, and wherein a bottommost one of the first channel layers is below a bottommost one of the second channel layers,
wherein a top surface of one of the first source/drain features is level with a top surface of one of the second source/drain features,
wherein the backside dielectric layer interfaces bottom surfaces of the first gate stack and the second gate stack as well as sidewalls of the first dielectric feature and the second dielectric feature,
wherein the first source/drain features and the second source/drain features partially extend into the backside dielectric layer.
2 . The multigate device of claim 1 , wherein a topmost one of the first channel layers and a topmost one of the second channel layers include a common top surface and a common bottom surface.
3 . The multigate device of claim 2 , wherein a top surface of the first gate stack and a top surface of the second gate stack are coplanar.
4 . The multigate device of claim 3 , wherein the bottom surface of the first gate stack is below the bottom surface of the second gate stack.
5 . The multigate device of claim 4 , wherein
the first FET further includes first inner spacers disposed horizontally on opposite edges of the first gate stack;
the second FET further includes second inner spacers disposed horizontally on opposite edges of the second gate stack;
the first inner spacers extend up to a first level; and
the second inner spacers extend up to a second level matching the first level.
6 . The multigate device of claim 5 , wherein
bottommost spacers of the first inner spacers are below bottommost spacers of the second inner spacers;
the bottommost spacers of the first inner spacers includes a first bottom surface being coplanar with the bottom surface of the first gate stack; and
the bottommost spacers of the second inner spacers includes a second bottom surface being coplanar with the bottom surface of the second gate stack.
7 . The multigate device of claim 6 , wherein
the second bottom surface is coplanar with the first bottom surface.
8 . The multigate device of claim 1 , further comprising a third FET disposed in a third region of the backside dielectric layer, wherein the third FET includes
third channel layers disposed over the backside dielectric layer,
a third gate stack disposed on the third channel layers and extended to warp around each of the third channel layers, and
third source/drain features interposed by the third gate stack and extended to contact the each of the third channel layers, wherein a number of the third channel layers is less than each of the number of the first channel layers and the number of the second channel layers.
9 . The multigate device of claim 1 , further comprising:
a first and second contact features connected to the first source/drain features, respectively; and
a third and fourth contact features connected to the second source/drain features, respectively, wherein the first and third contact features are disposed over top surfaces of the first source/drain features and the second source/drain features, and the second and fourth contact features are disposed below bottom surfaces of the first source/drain features and the second source/drain features.
10 . A multigate device comprising:
a backside dielectric layer having a first, second, and third regions;
a first field effect transistor (FET) disposed in the first region, wherein the first FET includes first channel layers disposed over the backside dielectric layer, a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers, first source/drain features interposed by the first gate stack and extended to contact the each of the first channel layers, and a first dielectric feature disposed below and interfacing a bottom surface of one of the first source/drain features;
a second FET disposed in the second region, wherein the second FET includes second channel layers disposed over the backside dielectric layer, a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers, second source/drain features interposed by the second gate stack and extended to contact the each of the second channel layers, and a second dielectric feature disposed below and interfacing a bottom surface of one of the second source/drain features; and
a third FET disposed in a third region, wherein the third FET includes third channel layers disposed over the backside dielectric layer, a third gate stack disposed on the third channel layers and extended to warp around each of the third channel layers, third source/drain features interposed by the third gate stack and extended to contact the each of the third channel layers, and a third dielectric feature disposed below and interfacing a bottom surface of one of the third source/drain features, wherein
a number of the first channel layers is greater than a number of the second channel layers,
the number of the second channel layers is greater than a number of the third channel layers, and
a topmost surface of the first channel layers is coplanar with a topmost surface of the second channel layers and a topmost surface of the third channel layers,
a portion of the third gate stack is sandwiched directly between a bottommost one of the third channel layers and the backside dielectric layer,
the backside dielectric layer interfaces bottom surfaces of the first gate stack, the second gate stack and the third gate stack,
the second source/drain features and the third source/drain features partially extend into the backside dielectric layer, and
bottom surfaces of the backside dielectric layer, the first dielectric feature, the second dielectric feature, and the third dielectric feature are coplanar.
11 . The multigate device of claim 10 , wherein
a bottommost surface of the first channel layers is below a bottommost surface of the second channel layers, and
the bottommost surface of the second channel layers is below a bottommost surface of the third channel layers.
12 . The multigate device of claim 11 , wherein a top surface of the first gate stack is coplanar with a top surface of the second gate stack and a top surface of the third gate stack.
13 . The multigate device of claim 12 , wherein
the bottom surface of the first gate stack is below the bottom surface of the second gate stack, and
the bottom surface of the second gate stack is below the bottom surface of the third gate stack.
14 . The multigate device of claim 10 , wherein
the number of the first channel layers is N, N being an integer greater than 3,
the number of the second channel layers is N−1, and
the number of the third channel layers is N−2.
15 . The multigate device of claim 10 , wherein top surfaces of the first source/drain features, the second source/drain features and the third source/drain features are coplanar.
16 . The multigate device of claim 10 , further comprising:
a first and second contact features connected to the first source/drain features; and
a third and fourth contact features connected to the second source/drain features, wherein the first and third contact features are disposed over top surfaces of the first source/drain features and the second source/drain features, and the second and fourth contact features are disposed below bottom surfaces of the first source/drain features and the second source/drain features.
17 . The multigate device of claim 10 , wherein
the first FET further includes first inner spacers disposed horizontally on opposite edges of the first gate stack and contacting the first source/drain features,
the second FET further includes second inner spacers disposed horizontally on opposite edges of the second gate stack and contacting the second source/drain features,
the first inner spacers vertically span between a first top surface and a first bottom surface,
the second inner spacers vertically span between a second top surface and a second bottom surface,
the first top surface and the second top surface are coplanar, and
the first bottom surface and the second bottom surface are coplanar.
18 . A multigate device comprising:
a backside dielectric layer having a first region and a second region;
a first field effect transistor (FET) disposed in the first region, wherein the first FET includes:
first channel layers disposed over the backside dielectric layer,
a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers,
first source/drain features interposed by the first gate stack and extended to contact the each of the first channel layers, and
a first dielectric feature disposed below and interfacing a bottom surface of one of the first source/drain features; and
a second FET disposed in the second region, wherein the second FET includes:
second channel layers disposed over the backside dielectric layer,
a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers,
second source/drain features interposed by the second gate stack and extended to contact the each of the second channel layers,
silicon features disposed on sidewalls of the second source/drain features such that each of the silicon features is disposed between one of the second source/drain features and the backside dielectric layer, and
a second dielectric feature disposed below and interfacing a bottom surface of one of the second source/drain features,
wherein a number of the first channel layers is greater than a number of the second channel layers,
wherein a bottommost one of the first channel layers is below a bottommost one of the second channel layers,
wherein a topmost one of the first channel layers and a topmost one of the second channel layers include a common top surface, and
wherein a bottom surface of one of the first source/drain features and a bottom surface of one of the second source/drain features are coplanar,
wherein the backside dielectric layer interfaces bottom surfaces of the first gate stack and the second gate stack as well as sidewalls of the first dielectric feature and the second dielectric feature,
wherein the first source/drain features and the second source/drain features partially extend into the backside dielectric layer.
19 . The multigate device of claim 18 , wherein
a top surface of the first gate stack and a top surface of the second gate stack are coplanar;
a bottom surface of the first gate stack is below a bottom surface of the second gate stack; and
the topmost one of the first channel layers and the topmost one of the second channel layers include a common bottom surface.
20 . The multigate device of claim 18 , wherein
the first FET further includes first inner spacers disposed horizontally on opposite edges of the first gate stack;
the second FET further includes second inner spacers disposed horizontally on opposite edges of the second gate stack;
the first inner spacers extend up to a first level; and
the second inner spacers extend up to a second level matching the first level.