Semiconductor package and method of manufacturing semiconductor package
A semiconductor package includes a package substrate, an interposer on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, the semiconductor devices being electrically connected to the interposer, a dam structure on the interposer extending along a peripheral region of the interposer, the dam structure being spaced apart from the semiconductor devices, and a stress relief on the interposer, the stress relief including an elastic member that fills gaps between the semiconductor devices and the dam structure.
1. A semiconductor package, comprising:
a package substrate;
an interposer on the package substrate;
a plurality of semiconductor devices on the interposer and spaced apart from each other, the semiconductor devices being electrically connected to the interposer;
a dam structure on the interposer extending along a peripheral region of the interposer, the dam structure being spaced apart from the semiconductor devices;
a stress relief structure on the interposer, the stress relief structure including an elastic member that fills gaps between the semiconductor devices and the dam structure; and
a first underfill member between the semiconductor devices and the interposer,
wherein the stress relief structure has increased elasticity relative to the first underfill member.
2. The semiconductor package of claim 1 , wherein a height of the dam structure is smaller than a height of the semiconductor devices.
3. The semiconductor package of claim 2 , wherein a width of the dam structure is within a range of 200 μm to 400 μm.
4. The semiconductor package of claim 1 , wherein a spacing distance between the semiconductor devices and the dam structure is within a range of 500 μm to 1,000 μm.
5. The semiconductor package of claim 1 , wherein the elastic member has an elastic modulus within a range of 2.0 GPa to 8.5 GPa.
6. The semiconductor package of claim 1 , wherein the elastic member includes an epoxy material.
7. The semiconductor package of claim 1 , further comprising:
a second underfill member between the interposer and the package substrate.
8. The semiconductor package of claim 1 , wherein the dam structure includes a silicon material.
9. The semiconductor package of claim 1 , wherein an outer surface of the dam structure is coplanar with an outer surface of the interposer, and
wherein a height of the dam structure is smaller than a height of the semiconductor devices.
10. A semiconductor package, comprising:
a package substrate;
an interposer on the package substrate, the interposer having a plurality of first and second bonding pads disposed respectively on a first surface and an opposite second surface of the interposer and electrically connected to each other;
a plurality of semiconductor devices on the first surface of the interposer and spaced apart from each other, the semiconductor devices being electrically connected to the first bonding pads;
a dam structure on the first surface of the interposer extending along a peripheral region of the interposer, the dam structure being spaced apart from the semiconductor devices;
a stress relief structure on the first surface of the interposer including an elastic member that fills gaps between the semiconductor devices and the dam structure; and
a first underfill member between the semiconductor devices and the first surface of the interposer,
wherein an outer surface of the dam structure is coplanar with an outer surface of the interposer, and
wherein a height of the dam structure is smaller than a height of the semiconductor devices.
11. The semiconductor package of claim 10 , wherein a width of the dam structure is within a range of 200 μm to 400 μm.
12. The semiconductor package of claim 10 , wherein a spacing distance between the semiconductor devices and the dam structure is within a range of 500 μm to 1,000 μm.
13. The semiconductor package of claim 10 , wherein the elastic member is integral with the first underfill member.
14. The semiconductor package of claim 10 , further comprising:
a second underfill member between the second surface of the interposer and the package substrate.
15. The semiconductor package of claim 10 , wherein the stress relief structure has increased elasticity relative to the first underfill member.
16. A semiconductor package, comprising:
a package substrate;
an interposer on the package substrate;
a plurality of semiconductor devices on the interposer and spaced apart from each other;
a first underfill member between each of the semiconductor devices and the interposer;
a dam structure on the interposer and extending along a peripheral region of the interposer, the dam structure being spaced apart from the semiconductor devices;
a stress relief structure on the interposer including an elastic member that fills gaps between the semiconductor devices and the dam structure;
a second underfill member between the interposer and the package substrate; and
a heat slug on the package substrate, the heat slug covering and thermally contacting the semiconductor devices,
wherein a width of the dam structure is within a range of 200 μm to 400 μm, and
wherein the stress relief structure has increased elasticity relative to the first underfill member.
17. The semiconductor package of claim 16 , wherein the dam structure includes a silicon material.
18. The semiconductor package of claim 16 , wherein a spacing distance between the semiconductor devices and the dam structure is within a range of 500 μm to 1,000 μm.
19. The semiconductor package of claim 16 , wherein the elastic member has an elastic modulus within a range of 2.0 GPa to 8.5 GPa.
20. The semiconductor package of claim 16 , wherein an outer surface of the dam structure is coplanar with an outer surface of the interposer, and
wherein a height of the dam structure is smaller than a height of the semiconductor devices.