Substrate-less diode, bipolar and feedthrough integrated circuit structures
Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.
1 . A substrate-less integrated circuit structure, comprising:
a single semiconductor fin;
a plurality of gate structures over the single semiconductor fin, each of the plurality of gate structures comprising a conductive gate electrode;
a plurality of P-type epitaxial structures over the single semiconductor fin;
a plurality of N-type epitaxial structures over the single semiconductor fin;
one or more open locations between corresponding ones of the plurality of gate structures; and
a backside contact connected directly to one of the epitaxial structures of the pluralities of P-type or N-type epitaxial structures.
2 . The substrate-less integrated circuit structure of claim 1 , wherein the substrate-less integrated circuit structure is a lateral diode, a bipolar device or a feedthrough device.
3 . The substrate-less integrated circuit structure of claim 1 , wherein the P-type epitaxial structures are boron-doped silicon or boron-doped silicon germanium structures.
4 . The substrate-less integrated circuit structure of claim 1 , wherein the N-type epitaxial structures are phosphorous-doped silicon structures.
5 . A computing device, comprising:
a board; and
a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
a single semiconductor fin;
a plurality of gate structures over the single semiconductor fin, each of the plurality of gate structures comprising a conductive gate electrode;
a plurality of P-type epitaxial structures over the single semiconductor fin;
a plurality of N-type epitaxial structures over the single semiconductor fin;
one or more open locations between corresponding ones of the plurality of gate structures; and
a backside contact connected directly to one of the epitaxial structures of the pluralities of P-type or N-type epitaxial structures.
6 . The computing device of claim 5 , further comprising:
a memory coupled to the board.
7 . The computing device of claim 5 , further comprising:
a communication chip coupled to the board.
8 . The computing device of claim 5 , wherein the component is a packaged integrated circuit die.
9 . The computing device of claim 5 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
10 . A substrate-less integrated circuit structure, comprising:
a single semiconductor fin;
a plurality of gate structures over the single semiconductor fin, each of the plurality of gate structures comprising a conductive gate electrode;
and a plurality of P-type epitaxial structures and N-type epitaxial structures alternating with ones of the plurality of gate structures,
the plurality of P-type epitaxial structures over the single semiconductor fin;
the plurality of N-type epitaxial structures over the single semiconductor fin;
wherein a pair of the N-type epitaxial structures is between a first of the P-type epitaxial structures and a second of the P-type epitaxial structures,
and a corresponding one or more open locations is between neighboring P-type epitaxial structures and N-type epitaxial structures.
11 . The substrate-less integrated circuit structure of claim 10 , wherein the pair of the N-type epitaxial structures is over an N-doped region of the single semiconductor fin.
12 . The substrate-less integrated circuit structure of claim 10 , wherein the substrate-less integrated circuit structure is a lateral diode.
13 . The substrate-less integrated circuit structure of claim 10 , wherein the P-type epitaxial structures are boron-doped silicon or boron-doped silicon germanium structures.
14 . The substrate-less integrated circuit structure of claim 10 , wherein the N-type epitaxial structures are phosphorous-doped silicon structures.
15 . A computing device, comprising:
aboard;
and a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
a single semiconductor fin;
a plurality of gate structures over the single semiconductor fin island, each of the plurality of gate structures comprising a conductive gate electrode;
and a plurality of P-type epitaxial structures and N-type epitaxial structures alternating with ones of the plurality of gate structures,
the plurality of P-type epitaxial structures over the single semiconductor fin;
the plurality of N-type epitaxial structures over the single semiconductor fin;
wherein a pair of the N-type epitaxial structures is between a first of the P-type epitaxial structures and a second of the P-type epitaxial structures,
and a corresponding one or more open locations is between neighboring P-type epitaxial structures and N-type epitaxial structures.
16 . The computing device of claim 15 , further comprising:
a memory coupled to the board.
17 . The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
18 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.
19 . The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.